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UID:dac_DAC 2024_sess232_ETPOST047@linklings.com
SUMMARY:Leveraging several automated techniques and methodologies for fast
 er coverage closure and design sign-off
DESCRIPTION:Engineering Track Poster\n\nGulshan Sharma and Sougata Bhattac
 harjee (Samsung)\n\nBottlenecks in Design verification sign-off process du
 ring project execution: \n    1. Coverage closure \n    2. Regression mana
 gement  \nProblems faced during Coverage closure :\n     1. Multiple itera
 tions of regressions\n     2. Covering all the bins (Lakhs of bins in curr
 ent RTL designs)\n     3. Analyzing the uncovered bins \nThe motivation fo
 r writing this paper is to create awareness and introduce the automated te
 chniques which saves iterations and execution time of DV engineer and make
  his life easier with reduced efforts for closing coverage\nThe presentati
 on explains several such techniques and along the way also mentions differ
 ent best practices that need to be followed within the test bench infrastr
 ucture for faster coverage and regression closure and also to catch the ma
 ximum number of bugs.\nLeveraging Portable stimulus standard (PSS) for fas
 ter functional coverage closure and constraints offloading.\n\nTopic: Back
 -End Design, Embedded Systems, Front-End Design, IP
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