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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST053@linklings.com
SUMMARY:Charting Uncharted Waters: Functional Simulation Reshaping CDC/RDC
  Constraints Signoff
DESCRIPTION:Engineering Track Poster\n\nsuhas S, Deepmala Sachan, Ponsanka
 r Arumugam, and Ritesh Jain (Intel Corporation)\n\nClock Domain Crossing (
 CDC)and Reset Domain crossing(RDC) checks signoff poses several challenges
  in digital design, and addressing these challenges is crucial for ensurin
 g the reliability and correctness of complex SoC's. While static analysis 
 tools provide critical role in CDC/ RDC analysis, functional verification 
 through simulations is equally necessary to validate the correctness of ar
 chitectural assumptions to signoff the correctness of static analysis. \nC
 urrent CDC/RDC constraints signoff challenges:\nAccuracy of constraints : 
 CDC/RDC constraints used for static analysis gets written based on certain
  design assumptions but what if these assumptions are incorrect . \nThorou
 ghness of constraints : What if these assumptions are not complete  ? \nVa
 lidation of constraints : Existing flow doesn't ensure the validity of the
 se constrains. \nFundamental goal of this presentation is to provide holis
 tic methodology for CDC/RDC constraints signoff which has been written bas
 ed on design assumption using SystemVerilog Assertions(SVA) in functional 
 simulations.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design
 , IP
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