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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST061@linklings.com
SUMMARY:Early Clock Tree Power Estimation and Correlation at SoC: A Case S
 tudy
DESCRIPTION:Engineering Track Poster\n\nSri Sai Pavan Pasumarthi, Sudheer 
 Yadapalli, and Vineet Ooramkumarath (Qualcomm)\n\nClock trees significantl
 y contribute to the overall power consumption of a design, accounting for 
 approximately 30-40% of the total power. Effectively estimating and analyz
 ing clock power at the System-on-Chip (SoC) level is crucial for identifyi
 ng and optimizing weak areas in the design. The identification of power bu
 gs prompts the exploration of various Clock Gating Strategies to enhance p
 ower efficiency.\n\nExisting methods for clock tree power estimation at th
 e gate level exhibit dependencies on processes like clock tree synthesis (
 CTS). However, these dependencies, occurring late in the cycle, hinder des
 ign optimization within the strict timelines of the SoC. Close to Base Tap
 e-out (BTO), attempting design optimization becomes more challenging, as c
 hanges can disrupt established timelines.\n\nThis paper introduces a pione
 ering workflow for early clock power estimation, providing feedback to cor
 es/IPs at the Register Transfer Level (RTL) stage. This approach aims to a
 ddress the limitations of current methods and emphasizes a proactive strat
 egy for optimizing clock power in the early stages of design, thus overcom
 ing the constraints imposed by late-cycle dependencies and stringent timel
 ines.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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