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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST064@linklings.com
SUMMARY:A Novel methodology for re-simulation of block vectors helping val
 idate Power Optimization QoR 20x faster
DESCRIPTION:Engineering Track Poster\n\nBhupesh Prajapat, Parul Dohare, Pr
 atik Talekar, Manish Kumar, Divya Parihar, Sachin Kumar, Mahima Jain, and 
 Mohammed Fahad (Siemens)\n\nTo achieve the highest power savings, it is de
 sired to make modification as early as possible in the design cycle requir
 ing RTL Power Optimization flows. One of the major challenges with RTL Pow
 er Optimization is lack of eco-system to validate the impact on Power for 
 the changes. To capture the power saving for modifications, new waveform m
 ust be generated, requiring a re-simulation. In most cases the simulation 
 setup is available for SoC, thus doing the re-simulation for modified RTL 
 becomes resource and time-consuming process. \n\nTopic: Back-End Design, E
 mbedded Systems, Front-End Design, IP
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