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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST090@linklings.com
SUMMARY:CDC Simulation Checker Implementation for Constant and Quasi-stati
 c Data Paths
DESCRIPTION:Engineering Track Poster\n\nYoungchan Lee (Samsung)\n\nIn the 
 structural sign-off of metastability issues associated with Clock Domain C
 rossings (CDC), several assumptions are made, one of which is the presence
  of static signals. Static signals are typically categorized into two type
 s: stable and constant. During the CDC structural sign-off process, these 
 static signals can obscure numerous asynchronous boundaries within data pa
 ths because they are presumed to be inherently safe.\nHowever, the validit
 y of such assumptions can be questionable, potentially leading to discrepa
 ncies when compared to functional sign-off. This underscores the necessity
  for a robust methodology to authenticate these presumptions.\nConventiona
 lly, the disparity between structural and functional sign-offs is mitigate
 d by validating assertions that focus on constrained signals. Yet, this tr
 aditional approach has limited analytical reach and fails to elucidate the
  issues clearly when assertions do not hold true. Its reliability is compr
 omised as it does not adequately address the metastability concerns that a
 rise when a static signal undergoes alterations at the fanout receiving re
 gisters across different clock domains.\nThis paper proposes a novel metho
 d for verifying data stability in static signals, aiming to enhance the re
 liability of CDC sign-offs by providing a more comprehensive analysis of p
 otential metastability issues. And also we explain that we can overcome th
 e simulation overhead with checkers embedded by way of re-organizing check
 er architecture algorithmically.\n\nTopic: Back-End Design, Embedded Syste
 ms, Front-End Design, IP
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