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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST105@linklings.com
SUMMARY:A "Shift-Left" Analysis Flow For Layout Parasitics Of High Speed A
 nalog Mixed Signal Design
DESCRIPTION:Engineering Track Poster\n\nwei wei, Yaping Huang, and Jie Hu 
 (Sanechips Technology Co.,Ltd); Xiaomei You (Ansys); and Wei Wei (Sanechip
 s Technology Co.,Ltd)\n\nFor today's high speed AMS design, as the process
 es shrinking and design complexity increasing, the layout parasitics have 
 become more and more important and even more dominant than devices, which 
 impact a lot on design's performance.On the other hand, as the parasitics 
 magnitude increase, it's more and more hard to debug complex parasitics is
 sue through traditional method like post-sim, with which designer need to 
 spend more post-sim and sign-off runtime, more experience-based manually d
 ebug and iteration to identify the real bottleneck can usually make the de
 sign schedule out of control.\nTo improve the design efficiency, a "shift-
 left" parasitic analysis flow for AMS layout parasitics become necessary a
 nd important, to help design identify the parasitics caused design problem
  more early, quickly, and easily.\nBefore go to sign-off stage, we first u
 se ParagonX perform quickly parasitics analysis of R, C, RC delay, net mat
 ching, etc in early design stage, and debug result by element, by layer, b
 y layout locations, to identify and optimize the real layout bottleneck, r
 educing the layout iterations ranging from weeks to hours. Through the flo
 w improvement, we makes parasitics debugging and layout optimization easy 
 and efficient, significantly improve design efficiency.\n\nTopic: Back-End
  Design, Embedded Systems, Front-End Design, IP
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