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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST108@linklings.com
SUMMARY:Electromagnetic Solutions From Design to Sign-Off Stage For High-S
 peed SerDes Design
DESCRIPTION:Engineering Track Poster\n\nYuhang Zhao, JinRong Yan, Hang Sun
 , and Xuewei Ding (Sanechips Technology Co.,Ltd) and Xiaomei You and Rodge
 r Luo (Ansys)\n\nIn high-speed SerDes design, to understand the EMag(elect
 romagnetic) coupling between various elements of a high-frequency semicond
 uctor device is very important, these EMag interactions include not only t
 he silicon chip but also extend to the package that encloses it. At sign-o
 ff phase, it is common to find that block level pre-lvs EMag simulation re
 sult shows big difference when compare with measurement data, it is very n
 ecessary and important to perform EMag simulation at sign-off phase to red
 uce the gap.\n    Traditional EMag simulations method only consider chip c
 oupling and not the packaging layers with on-chip metals model, that may l
 ead to design specification violations. Traditional EMag flow only extract
  layout with passive devices, if EMag coupling is not fully considered, it
  will lead to a large mismatch between post-lvs simulation result and meas
 urement.\n    In high-speed SerDes design, high-precision and high-efficie
 ncy electromagnetic modeling simulation is required to minimizing the asso
 ciated EMag risks. RaptorH die+package modeling flow can predict the impac
 t of EMag coupling with package layers at block stage; Exalto post-lvs EMa
 g simulation can resolve mismatch between post-simulation and measurement 
 at sign-off stage; and finally increase confidence in the performance of h
 igh-speed SerDes design.\n\nTopic: Back-End Design, Embedded Systems, Fron
 t-End Design, IP
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