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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST111@linklings.com
SUMMARY:Systematic Verification Framework for Memory Subsystem Ensuring Re
 liability and Robustness
DESCRIPTION:Engineering Track Poster\n\nVatsal Patel, Pooja Patel, Dharini
  SubashChandran, Ritesh Desai, and Pratibha Sukhija (Cadence Design System
 s, Inc.)\n\nThe vertical segments across IoT, data centers, AI, networking
 , autonomous vehicles, cryptocurrency infrastructure are creating data req
 uirements explosion. New standards, emerging at lightning speeds, are batt
 ling the never-ending thirst for low power, high speed and throughput. Wit
 h the increase in complexity, the verification effort is also increasing e
 xponentially. Multiple DRAM memory vendors and wide varieties of memory ar
 e growing challenges as each vendor have their own unique timing parameter
  types/ values and configuration register values. Ensuring the correctness
  of timing parameter values and registers so that the DDR Controller, DDR 
 PHY, and the DRAM device operate in sync is a huge and error-prone task. T
 o make this effort error-free, we have developed an automated and scalable
  solution where the verification features of DFI and Memory are integrated
  and synced to reduce the verification efforts, fast time to market, and n
 o silicon escape.\n\nTopic: Back-End Design, Embedded Systems, Front-End D
 esign, IP
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