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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST114@linklings.com
SUMMARY:Developing Software Test Library (STL) as a Safety Mechanism for V
 ision AI DSP
DESCRIPTION:Engineering Track Poster\n\nNoam Meser and Zvika Melamed (Ceva
  Technologies, Ltd.) and Sesha Sai Kumar C V, Ayman Mouallem, and Fares Ja
 raisy (Optima Design Automation Ltd)\n\nCeva SensPro AI & Vision DSP are e
 mbedded within automotive and many other markets' chips that require safet
 y. Showing that DSP matches the safety metrics set by ISO 26262 for releva
 nt ASIL is critical across these markets as they move towards having advan
 ced ADAS and autonomous driving solutions. STL is a state-of-the-art SW-ba
 sed safety mechanism which allows DSP to address ASIL KPIs specifically ta
 rgeting permanent HW faults. \n\nThe DSP cores are developed as SEooC (gen
 eric off the shelf IP), with ASIL B integrity level. This paper discusses 
 the challenges in developing the STL with RTL design and fault injection a
 nalysis, in achieving the SPFM for identified modules based on Technical S
 afety Requirements. Also highlighted are various challenges involving coll
 aboration between multiple teams – SW, HW, PM and Safety.  An ISO 26262 ce
 rtified fault injection analysis tool and methodology is used to generate 
 various results and customized reports to effectively iterate and improve 
 the STL to achieve the required targets of SPFM.  \n\nCustomized reports, 
 from the tool has helped in clearly communicating the improvements needed 
 for STL to reach the target Diagnostic Coverage and SPFM, like faults that
  are blocked by various configuration registers, which constants flops to 
 be toggled to make STL more effective, time taken to detect fault after in
 jection, SPFM for individual modules and all combined.\n\nTopic: Back-End 
 Design, Embedded Systems, Front-End Design, IP
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