BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST119@linklings.com
SUMMARY:Methodology of linking the LDR and DRC code by automatically gener
 ated test pattern
DESCRIPTION:Engineering Track Poster\n\nDongjin Kim, Kwonjae Kim, Seyeon M
 oon, Boyoung Lee, Youngwook Kim, and Jungyun Choi (Samsung)\n\nAs for the 
 advancements in the fabrication process, Integrated Circuits (ICs) blocks 
 are complicatedly designed. One of the main verification method verifying 
 the layout using Design Rule Check (DRC) is commonly adopted. DRC is coded
  by the DRC team understanding the intention of Layout Design Rule (LDR) w
 hich is issued by the process engineer. One of the challenges faced betwee
 n the LDR and DRC is insufficient information. The link between the LDR de
 scription and the DRC code is the key factor for preventing accident and t
 urnaround time. Generating LDR based test pattern layout automatically ena
 bles to checks intention between DRC code and LDR. For verifying complicat
 ed derived layers and cell based test patterns are also needed which requi
 res updating standardized descriptions. Analyzing the result of DRC error 
 from the test pattern strengthens the LDR description and checks the DRC c
 ode correctness. We provide solution for standardization, automation flow 
 between the LDR description and DRC code for quality assurance with reduce
 d time.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
END:VEVENT
END:VCALENDAR