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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST125@linklings.com
SUMMARY:Memory Clusters – Divide the design and optimize MBIST insertion e
 fforts
DESCRIPTION:Engineering Track Poster\n\nSanthosh Ramappa (Marvell) and Sub
 hash Baraiya (Marvell India Pvt. Ltd.)\n\nProblem Statement : Modern appli
 cations demand memory intensive complex SOC's with tighter time to market 
 schedules. For such designs; implementing high quality test and repair sol
 ution is a unique challenge to achieve with optimum mbist insertion effort
 s. Traditional MBIST insertion methods needs multiple MBIST insertion runs
  as many times as functional RTL or netlist changes. This keeps DFT team e
 ngaged running mbist insertion multiple times. \n\nApproach/Methodology : 
 \nIn this paper, we've broadly covered optimize design practices which hel
 ps reducing mbist insertion iterations. The design hierarchies are partiti
 oned  into memory clusters such a way that the mbist insertion is required
  only if there are memory changes in the given cluster. The flow is create
 d such that the functional connections remains intact and only the bist pi
 ns of memories get hooked up to BIST logic. This avoids any mbist intercep
 ts in functional paths. Different experiments are done to achieve optimum 
 area, power, timing closure and bist runtimes. \n\nWhen performing the DFT
  insertion flow with sub-blocks, you insert MemoryBIST and pre-DFT DRCs at
  the sub-block level and then move up to the sub-block's next parent physi
 cal block level (where the sub-block is instantiated) to perform ICL extra
 ction/Synthesis/Scan insertion. \n\nImpact/Results : \n         Multiple i
 nstantiations — You only need to perform the DFT insertion flow once for a
  sub-block. Thereafter, every instantiation of the sub-block includes the 
 inserted DFT hardware\nSmall size — Most sub-blocks are not big enough to 
 be considered their own physical regions which saves run time\nReadiness —
  Sometimes the sub-block RTL is complete before the RTL for the physical l
 ayout region, thus you can begin DFT insertion on the sub-block as soon as
  RTL is ready\n\nTopic: Back-End Design, Embedded Systems, Front-End Desig
 n, IP
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