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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST129@linklings.com
SUMMARY:Design Automation of Minimal Layer Count Microprocessor 2.5D Silic
 on Interposer
DESCRIPTION:Engineering Track Poster\n\nOmer Vikinski, Basil Tarabiea, and
  Alexander Waizman (Intel Corporation)\n\nIntel latest microprocessors are
  built by chiplet assembly over Foveros passive silicon interposer. Second
  generation based on this technology was targeting a more aggressive cost 
 optimization, featuring reduced interposer layer count and decoupling dens
 ity. Stronger design automation flows were developed, minimizing the manua
 l layout labor, and tuned to address the inherent challenges of reduced la
 yer count interposer. The design automation flow consists of few key stage
 s, some of them logistics and some carry the algorithms for the layout syn
 thesis. Among those synthesis algorithms is voltage area automatic generat
 ion, which set the regions for power delivery grid stenciling and decoupli
 ng spread. Another algorithm is pad-to-pad robust via connectivity, enable
 d to withstand slight offsets between the interposer bumps, and to mediate
  the connectivity of the pad with the rest of the power delivery grid. Alt
 hough some manual user interventions are allowed, and some manual or semi 
 manual layout editing is recommended, all manual steps are registered and 
 archived to allow automatic re-run iterations. Finally, the full database 
 can be built within few hours of uninterrupted flow. The database is meeti
 ng all design criterions (manufacturing, reliability, timing), minimizing 
 the need of manual layout design, and meeting schedule by the efficient ru
 n times.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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