BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST131@linklings.com
SUMMARY:Predicting Computer Resource Needs using Machine Learning and Conv
 entional Design
DESCRIPTION:Engineering Track Poster\n\nJustin Conklin (Marvell)\n\nToday,
  the semiconductor design industry is centered around the use of EDA tools
 . These tools provide the necessary information and automation for a desig
 n engineer to do their work effectively. The automation of design processe
 s is especially significant and has been key to the success of the industr
 y. However, process automation comes at the cost of large compute resource
  requirements. These requirements will only increase as the industry conti
 nues to automate more processes. Therefore, the way a semiconductor design
  company manages their compute resources is and will continue to be essent
 ial to their success.\n\nThis presentation describes the details of two sy
 stems developed for predicting EDA tool resource usage. The first relying 
 on a more conventionally engineered "recently used" algorithm and the seco
 nd centered around a machine learning framework. Covered topics will inclu
 de comparisons of algorithm complexity and accuracy in key compute resourc
 es such as memory usage.\n\nTopic: Back-End Design, Embedded Systems, Fron
 t-End Design, IP
END:VEVENT
END:VCALENDAR