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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST132@linklings.com
SUMMARY:3DIC prototype design and transient early thermal analysis
DESCRIPTION:Engineering Track Poster\n\nYongjin Hong, Kiwook Jung, Ki-Ok K
 im, Byunghyun Lee, and Sangyun Kim (Samsung)\n\n3DIC design can reduce the
  length of interconnections and secure gains in power and performance by u
 sing multiple dies stacked vertically.\nHowever, the design complexity inc
 reases, and more resources are required to modify the design compared to a
  single die design.\nIn the early stages of design, we need to be able to 
 quickly and easily prototype design.\nEarly thermal analysis is an importa
 nt key to determining the design floorplan, and a high correlation is requ
 ired after the design is complete.\nWhen we performed thermal analysis on 
 the prototype design and the two designs after the actual P&R was complete
 d, we confirmed that the thermal map showed similar heat maps and hot spot
 s.\nWhen we performed thermal analysis according to the three power scenar
 io steps, the largest error rate between the prototype and the real was 8.
 34%, which was found near the chip boundary at 5.8s.\n We confirmed that t
 he temperature difference was less than 10% and the hot spot trend was ver
 y similar.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, 
 IP
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