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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST135@linklings.com
SUMMARY:Areal and Time Decomposed Phalanx based Dynamic IR-Drop Prediction
  using DNN(Deep Neural Network) at Earlier stage of Design cycle
DESCRIPTION:Engineering Track Poster\n\nSeihyung Jang, Gyusun Park, Kibum 
 Kang, Yun Ra, Kisun Kim, Kisik Lee, Changsik Lee, and Hongsok Choi (SK hyn
 ix) and Taejin Kim, Hongpa Che, and Dongchul Kang (Cadence Design Systems,
  Inc.)\n\nAs the semiconductor technology has been increased, a lot of cha
 llenges related to IR-Drop have been increased considerably in recent year
 s. Especially Dynamic IR-Drop issue becomes a bigger factor resulting in f
 unction failure and this will be true for advanced process node below 5nm 
 and smaller. We need post-VCD files having various actual scenarios to fin
 d out if there are IR-Drop issues or not. But this post-VCD files can't be
  available until the end of design cycle and this is too late to fix out I
 R-Drop issues. It's very time consuming, painful and sometimes almost impo
 ssible to fix out at the final stage of design cycle when the post-VCD fil
 es can be obtainable.\n\nThe only to resolve this situation is to find out
  where is weak to dynamic IR-Drop as earlier as possible and that's why we
  have proposed the Areal and Time decomposed Phalanx based DNN(Deep Neural
  Network) methodology. Using this methodology, we have chosen Phalanx whic
 h is most similar to DNN modeling and predicted IR-Drop at the new design.
  We have found out where is weak at PDN(Power Distribution Network) even w
 ithout layout routing information which is essential in the traditional fl
 ow and can fix out issues and strengthen PDN at the very earlier stage of 
 design cycle with this methodology. \n\nThis method shows a IR-Drop accura
 cy over 95% and reduced a lot of iteration time to fix IR-Drop violation b
 y 40% or so.\n\nThis Areal and Time decomposed Phalanx based DNN methodolo
 gy has been verified using commercial tool, Cadence Voltus.\n\nTopic: Back
 -End Design, Embedded Systems, Front-End Design, IP
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