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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST137@linklings.com
SUMMARY:Automated Floorplan Scaling Solutions and Framework
DESCRIPTION:Engineering Track Poster\n\nSivaramakrishnan Harihara Subraman
 ian, Venkatesh RS, and Khris Valencia Chacon (Intel Corporation)\n\nConven
 tional hierarchical design planning flows are neither runtime efficient no
 r resource efficient for a) quick floorplan porting during process node ev
 aluation and library bring up with minimal dependency or b) what-if explor
 ation to hasten block convergence with improved local FP optimization and 
 identify critical limiters for different partition layout topologies. The 
 scaling framework is a one-stop solution capable of operating on bare mini
 mum baseline floorplan information to port floorplans even without any net
 list or memory collaterals. The Framework can generate basic floorplanning
  compatible netlist and scaled library memory collateral from baseline flo
 orplans on a different node/library. The framework can also enable evaluat
 ion of block convergence recipes and floorplan utilization or frequency sw
 eeps through macro placement techniques including ML macro placement suita
 bly augmented with additional algorithmic pin placement intelligence to re
 tain global context. The framework has evolved to be the de facto early fl
 oorplan execution flow, scaling and porting floorplans between libraries, 
 nodes and even foundries, and improving the work model execution efficienc
 y by 16X and resource efficiency by 3X for each partition. The framework h
 as also been a key pillar in block optimization exploration, during later 
 execution milestones, saving 2-4 weeks of convergence efforts on 80% of bl
 ocks with pre-configured techniques and strategies.\n\nTopic: Back-End Des
 ign, Embedded Systems, Front-End Design, IP
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