BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST141@linklings.com
SUMMARY:Reducing Interlayer misalignment caused by BLE (Bulk Layout Effect
 ) : Solutions for improving in-chip uniformity of alignment between two la
 yers
DESCRIPTION:Engineering Track Poster\n\nHyejin Kim, Ohhun Kwon, Jichang Si
 m, Daehee Lee, Hyunmi Ji, and Jooseong Lee (Samsung)\n\nAs DRAM devices co
 ntinue to shrink, defects that are out of tolerance have become more preva
 lent. One such defect is interlayer misalignment, which occurs when two la
 yers are not aligned correctly. Interlayer misalignment caused by the shif
 ted patterns due to heat and stress is called as BLE (Bulk Layout Effect).
  It can lead to poor device yield.\nIn this paper, we propose two correcti
 on methods to reduce interlayer misalignment caused by BLE. The first meth
 od involves correcting the mask where BLE occurs in the opposite direction
  of the BLE. The second method involves correcting the other mask affected
  by BLE in the direction of the BLE. One of these methods should be chosen
  to ensure that it does not interfere with layout connections.\nWe evaluat
 ed methods using two different items. The interlayer misalignment in the c
 hip decreased by 89% and 58% in item #1 and item #2, respectively. In addi
 tion, in-chip uniformity of alignment improved by 25% in item #1 and 27.4%
  in item #2.\nIt is proved that reducing interlayer misalignment caused by
  BLE can help improve in-chip uniformity of alignment. And it is expected 
 to contribute to improving device yield by widening the window of manufact
 uring process tolerance.\n\nTopic: Back-End Design, Embedded Systems, Fron
 t-End Design, IP
END:VEVENT
END:VCALENDAR