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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST144@linklings.com
SUMMARY:Timing Closure Methods on 5nm Design Challenges
DESCRIPTION:Engineering Track Poster\n\nPatricia Fong (Marvell)\n\nHold ti
 ming violations can be challenging to fix especially with additional limit
 ations in a 5nm design that were not seen in larger nodes, such as power, 
 crosstalk, and narrower setup-hold window (less setup margin). Current Pla
 ce and Route (PnR) and timing eco tools struggle to address these difficul
 t hold violations due to the use of limited timing views for acceptable ru
 ntime and the tendency to insert excess hold padding that may have issues 
 with wiring and power. This presentation describes four methods that can r
 educe hold violations with a less impact on power and wiring resources. Th
 e methods are: Reducing the VT on the existing cells, reducing the drive s
 trength on existing cells, placing delay cells further away that is less c
 ongested and with wiring resources, and manipulating the clock so there wo
 uld be less hold violations due to a wide clock skew. These methods provid
 e additional solutions besides the traditional padding method so that the 
 timing closure is not deadlocked with power and wiring issues.\n\nTopic: B
 ack-End Design, Embedded Systems, Front-End Design, IP
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