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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST147@linklings.com
SUMMARY:Systematic Flow on AC Scan Timing/ATPG Constraint Generation
DESCRIPTION:Engineering Track Poster\n\nChen Yuan Kao and Yi Hsuan Chiu (G
 lobal Unichip Corporation)\n\nDFT engineers take efforts on high quality S
 DC delivery in limited schedule for timing analysis and ATPG. To meet the 
 schedule, engineer often got quality loss on false path consistency due to
  limited schedule or human error causing coverage loss or time wasted on t
 iming violation review. APR timing closure progress will also be impacted.
  Moreover, function constraint is often updated during timing closure prog
 ress. Function constraint cannot be directly used in AC scan and referenci
 ng timing report to prepare AC scan constraint often sacrifice test covera
 ge. Preparing AC scan constraint often takes time and rely on DFT engineer
 's experience to ensure the constraint quality.\nWe provided a systematic 
 flow to generate AC scan timing and ATPG constraint dealing with clock str
 ucture difference, unsupported description due to ATPG tool limitation, mu
 ltiple test mode for ATPG, and add-on/redundant timing exception due to Sc
 an structure. The flow helps map AC scan clocks to function clocks and gen
 erate AC scan timing and ATPG constraints efficiently.\n\nTopic: Back-End 
 Design, Embedded Systems, Front-End Design, IP
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