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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST149@linklings.com
SUMMARY:Bus Delay Skew Minimization for High Bandwidth Memory Designs
DESCRIPTION:Engineering Track Poster\n\nKwangok Jeong, Seoklip Ki, and Sua
  Kim (Samsung) and Alpesh Kothari, Jaejun Lee, JeongGuk Choi, Raghu Gude, 
 and Sung-Soon Choi (Siemens)\n\nHigh bandwidth memory (HBM) consists of se
 veral memory chips and a dedicated buffer die that serializes and de-seria
 lizes data for processing and transferring. One major parameter deciding t
 he performance of a buffer die is the number of parallel signal buslines s
 panning half the die between signal IO circuitry (e.g., PHY) and input/out
 put ports (i.e., through-silicon via (TSV)) of the buffer die. The speed o
 f signal buses is also important to make smoother signal transitions durin
 g the clock cycle time. This transition time ensuring full signal swing, d
 etermines the maximum clock frequency of the HBM. The faster the device an
 d the larger the number of buslines, the higher the performance an HBM can
  deliver. The busline bit count is expected to exceed several tens of thou
 sands in the next HBM generation. The busline delay difference must be min
 imized for correct signal transfer of all bits within a very narrow availa
 ble time slot for signal transition. Until now, the bus design has been do
 ne by iterative manual layout and simulation, since no good automated solu
 tions exist.This work seeks an automated layout and optimization methodolo
 gy for the many signal buslines for a next generation HBM. We formulate th
 e design constraints from custom layouts, and develop a novel bus delay op
 timization algorithm based on a commercial P&R tool. This automated soluti
 on demonstrates a bus layout for an HBM buffer die within seconds, while s
 atisfying all metric requirements.\n\nTopic: Back-End Design, Embedded Sys
 tems, Front-End Design, IP
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