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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST153@linklings.com
SUMMARY:Die-Level Dynamic-IR Analysis Shift-Left Enabled by RedHawk-SC Sig
 maDVD
DESCRIPTION:Engineering Track Poster\n\nRuiqi Wu (UNISOC); Ran Zhang, Luca
  Cui, and Chang Zhao (Ansys); and Marc Zheng (UNISOC)\n\nAs Silicon scalin
 g continue to reach into Angstrom domain, dimension scaling slows down. ho
 wever silicon feature and compute power stills continue to increase at rat
 e comparable to Moore's Law. Power Integrity is now becoming a key challen
 ge for sub nanometer processes. Die-level Power Integrity signoff is norma
 lly done at the final stage of IC design. Power-Plan design and synthesis 
 on the other hand are done before Automated-Place-And-Route (APR). A key c
 onundrum for Power Plan design and synthesis, is the lack of reference inf
 ormation, especially for new IP, such as a latest high-performance CPU. A 
 tapeout quality IR signoff for APR, requires a post-routed (final-stage) A
 PR database, a couple of post-layout simulation pattern which exercises th
 e logic to consume current from the on-die power-grid in a near-realistic 
 worst-case manner, an optimized package model which describe the package b
 all to bump impedance. All three critical input information for IR analysi
 s becomes available only at the end of the IC implementation process, posi
 ng risk to tapeout schedule and possible IC failures due to severe IR drop
 .  In this presentation, we demonstrate how Sigma-DVD resolve this conundr
 um, allowing our engineers to identify Dynamic-IR hotspots, without end-of
 -the-stage functional pattern, and hence "shift-left" to strengthen Power-
 plan on potential weak-spots, before the weak-spots gets identifed too lat
 e in the implantation process.\n\nTopic: Back-End Design, Embedded Systems
 , Front-End Design, IP
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