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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST155@linklings.com
SUMMARY:Machine-Learning-Driven Floorplan-Aware Power Delivery Network Co-
 Planning
DESCRIPTION:Engineering Track Poster\n\nBogdan Tabacaru (Infineon Technolo
 gies) and Jerome Toublanc (Ansys)\n\nEnabling new applications such as aut
 onomous driving or car architectures with centralized ECUs, heterogeneous 
 systems-on-chip (SoCs) with multiple CPUs, multi-level memory hierarchies,
  various co-processors and hardware accelerators is becoming a key archite
 ctural paradigm. Such highly dense automotive SoCs implemented in advanced
  CMOS technologies are sensitive to process-voltage-temperature variations
  and other physical disturbances. To mitigate increasing sensitivity chall
 enges of logic gates and memories to transient supply noise, temperature e
 ffects and process variations, robust-enough power-delivery networks (PDNs
 ) must be implemented. However, PDN development is facing its own challeng
 es such as late-stage sign-off during the SoC's development cycle, long si
 mulation times, computationally intensive simulations, and late discovery 
 of voltage-drop and electromigration violations when fixes are expensive t
 o implement. Furthermore, PDNs are typically initially defined without con
 sidering the package. To overcome these limitations, we propose a machine-
 learning-driven floorplan-aware power-co-planning methodology using Ansys'
  OptiSlang that shifts left the PDN development to the prototyping (archit
 ecture) abstraction level and enables automation of PDN die-package co-des
 ign and verification. Our solution transforms PDN development from a proce
 ss that produces a couple of simulation results using more than 10 experts
  in several months into one that compares more than 1000 results using a s
 ingle expert in a few days.\n\nTopic: Back-End Design, Embedded Systems, F
 ront-End Design, IP
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