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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST156@linklings.com
SUMMARY:Advanced LLE aware Timing Signoff Methodology
DESCRIPTION:Engineering Track Poster\n\nYoobeom Kim, Jingon Lee, Chul Rim,
  and Hyunseung Seo (Samsung) and Sangwoo Han, Ahmed Shebaita, Tajendra Sin
 gh, Li Ding, and Sunik Heo (Synopsys)\n\nThis presentation is about how to
  consider LLE impact in timing signoff flow. In advanced node, LLE impact 
 is increased than before, so it has become an essential item to be conside
 red.\nBecause this LLE impact could not be considered in timing signoff fl
 ow in the existing method, we introduce the advanced timing signoff method
 ology that fully considers LLE impact.\nLLE impact can be calculated with 
 vth and u0 parameters. So with sensitivity of these parameters characteriz
 ed library, depending on which cell is placed next to it, the amount of ch
 ange in these parameters are measured and reflected in the delay.\nAdditio
 nally, the verification method and design gain that can be obtained from t
 his methodology are also described.\n\nTopic: Back-End Design, Embedded Sy
 stems, Front-End Design, IP
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