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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST162@linklings.com
SUMMARY:Novel Way of Checking and Analyzing Peak to Peak Voltage Variation
  Challenges for High Computational Multiprocessors SOC
DESCRIPTION:Engineering Track Poster\n\nAmit Singh, Govind Pal, and Anil Y
 adav (STMicroelectronics) and Amit Jangra and Koshy John (Ansys)\n\nIncrea
 sing functionality of Automotive multiprocessor SOCs has resulted in incre
 asing power grid complexity leading to high voltage-ripple noise caused by
  simultaneous switching of multiple processor blocks in the SoC. Meeting c
 hip-package-system (CPS) performance targets becomes daunting due to this 
 issue. Designers grapple with the lack of accurate chip models for chip-pa
 ckage-system co-analysis for power integrity signoff involving microsecond
  long simulations. The conventional Chip Power Model (CPM) falls short in 
 addressing low frequency noise (0.1 – 50 MHz) caused during chip mode-chan
 ges over longer durations. Multiprocessor chips have high demand currents 
 that require techniques like clock and power gating to deal with excessive
  power requirement. However, Dynamic Voltage and Frequency Scaling (DVFS) 
 and clock gating can induce significant simultaneous switching noise (SSN)
  on VDD. We present here the results of our study that utilized advanced c
 hip power models involving time extensions, stitching of multiple models a
 nd modulation of high frequency chip currents over mode-changing low frequ
 ency current envelope, to help detect and mitigate high peak to peak volta
 ge variations in our chip-package-system transient analysis with a faster 
 turn-around-time.\n\nTopic: Back-End Design, Embedded Systems, Front-End D
 esign, IP
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