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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST173@linklings.com
SUMMARY:Automated Place and Route based solution for Custom Blocks
DESCRIPTION:Engineering Track Poster\n\nRajeev Singh and Atul Bhargava (ST
 Microelectronics); Akshita Bansal and Vishesh Kumar (Cadence Design System
 s, Inc.); and Vijay Singh Khati (STMicroelectronics)\n\nMost SoCs today ha
 ve analog or mixed signal blocks, such as SerDes cores, DACS, ADCs, PLLs a
 nd other transceivers. Many analog blocks have digital control logic. As s
 uch, an increasing amount of analog IP is mixed signal, and with rapidly i
 ncreasing SoC capacity, a single IP block might represent an extremely com
 plex mixed signal function. Currently, a sizable part of mixed signal desi
 gn implementation is done manually, which is a slow and laborious process 
 that can lead to design errors and numerous iterations. The blocks are pla
 ced and routed using semi-manual process, without the aid of design rule-c
 orrect automation. In this paper, we introduce a methodology to automate t
 he placement and routing of such digital/mixed signal blocks with LVS and 
 DRC awareness. Within a few clicks the digital block is placed and routed 
 with the addition of boundary cells, tap cells and fills. The solution is 
 capable to read user constraints and enhance quality of routing.\n\nTopic:
  Back-End Design, Embedded Systems, Front-End Design, IP
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