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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST174@linklings.com
SUMMARY:Design Closure Methodology using stage wise checkers by Ease of Re
 view to minimize Physical Design Implementation & Closure TAT
DESCRIPTION:Engineering Track Poster\n\nShilpi Srivastava, Daniel Hand, an
 d Jagadeesh Gnanasekaran (Intel Technologies India Private Ltd)\n\nAn effi
 cient and effective methodology for an overall turn around time reduction 
 during physical design implementation phase of SOC Design. This has been i
 mplemented via automated stagewise checkers and ease of review dashboard. 
 The smooth and ease of project execution involves data gathering during in
 itial design planning. The idea is to closely inspect the QOR of every phy
 sical design implementation stage and rework to achieve the best possible 
 results before passing on to next stage.\nThis would help in easy design c
 losure at final stage and effectively reduce the huge runtimes usually see
 n towards the last stages as more and more design components starts stacki
 ng up on the SOC.\n\nThe problem or pain point has been correctly identifi
 ed, and the proposed solution is capable of producing the desired outcomes
 . The stagewise data can be viewed in a user-friendly dashboard which furt
 her simplifies the tracking and review process. Further eliminating the sc
 ope of human error. During initial design phase working with dirty data wo
 uld lead to multiple check failures which can be reviewed and waived initi
 ally, but the same need to be attended during final closure. All this is p
 retty well captured and tracked. The dashboard is quiet helpful in reviewi
 ng  final design closure. It clearly gives the reviewer what all as passed
 /failed/waived at different stages. All the waivers have the justification
 s along with approver details.\n\nTopic: Back-End Design, Embedded Systems
 , Front-End Design, IP
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