BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST177@linklings.com
SUMMARY:Quality Assurance of DRC deck for Devices by SKILL Automation
DESCRIPTION:Engineering Track Poster\n\nAmbika Bhardwaj, Chirag Agarwal, P
 iyush Soni, and kancou traore (STMicroelectronics)\n\nThe quality of the P
 rocess Design Kit (PDK) is crucial for the success of any System-on-Chip (
 SOC) for any organization. Design Rule check is one of the mandatory check
 s in the sign-off process of a SOC or  an IP. The QAcell methodology invol
 ves exhaustively creating small layouts representing the violating and leg
 al configurations to verify the alignment of the Design Rule Check (DRC) d
 eck with the Design Rule Manual (DRM) separately for each rule, including 
 Device Rules. To increase the productivity , SKILL automation can automate
  the design of layout test cases (QAcells) for device rules. The automatio
 n allows quick and easy customization of complex devices and layouts with 
 varying CDF parameters. This automation reduces the validation engineer's 
 time by 3x for validating each rule separately. The combination of the QAc
 ell methodology and SKILL automation provides an efficient approach to ver
 ifying the quality of the DRC deck for Device Rules. The result is a faste
 r and precise validation methodology.\n\nTopic: Back-End Design, Embedded 
 Systems, Front-End Design, IP
END:VEVENT
END:VCALENDAR