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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST180@linklings.com
SUMMARY:Modeling Optimal Number of Tap-points for Flexible H-tree During C
 lock Tree Synthesis
DESCRIPTION:Engineering Track Poster\n\nAnup kumar and Akshay Mankotia (Ca
 dence Design Systems, Inc.)\n\nClock tree synthesis is the process of conn
 ecting the clocks to all clock pins of sequential circuits by using invert
 ers or buffers in order to balance the skew and minimize the insertion del
 ay. There are multiple techniques available for clock distribution. Some o
 f these methods include the single clock tree, multi-tap clock tree, clock
  mesh, and Flex H-Tree.\n\nFlex H-tree is a sophisticated methodology for 
 clock distribution that maintains electrical symmetry but is flexible in g
 eometrical symmetry. It helps in achieving the minimum skew in a clock tre
 e, relaxes the requirement to be geometrically symmetric, and automates sy
 nthesis even in floorplans with placement restrictions.\n\nFlexH-Tree enab
 les users to make smart latency vs. timing trade-offs. The classical probl
 em that designers face while building FlexH-Tree is the selection of the n
 umber of tap points.\nThere are an infinite number of combinations for tap
 -points.\n\nThis paper provides a noble approach to determining the optima
 l number of tap-points per clock library cells.\n\nTopic: Back-End Design,
  Embedded Systems, Front-End Design, IP
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