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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST185@linklings.com
SUMMARY:Balancing Power and Performance: The Hybrid Clock Network Approach
  for Network on chips
DESCRIPTION:Engineering Track Poster\n\nPallapu Lakshmi Sarvaani (Indian I
 nstitute of Technology, Tirupati) and Subba Annapalli and Ponnada Appala N
 aidu (Intel Technology India. Pvt. Ltd)\n\nIn the rapidly evolving landsca
 pe of technology, the pursuit of high-performance systems has become incre
 asingly essential. With the growing complexities in chip design, achieving
  a harmonious balance between Power, Performance, and Area (PPA) – the fou
 ndational pillars of contemporary chip architecture – presents formidable 
 challenges. Traditional clock methodologies such as clock tree synthesis, 
 clock mesh, and multi-source clock tree synthesis have proven inadequate i
 n addressing the intricacies of modern chip design. Recognizing these limi
 tations, we introduce the innovative Hybrid Clock Network technique, a cus
 tomized approach designed to construct robust clock networks within Networ
 k On Chips (NoC).\n\nOur technique has yielded remarkable improvements in 
 clock quality when compared to conventional clock tree methodologies. Nota
 bly, our results showcase a 41.66% reduction in latency, a 43.75% enhancem
 ent in skew, a 14.22% decrease in clock power consumption, and an overall 
 12.46% reduction in total power consumption. Additionally, our approach ha
 s conserved 11.55% of routing resources, reduced the clock buffer count by
  16.2%, and streamlined the clock depth from 23 to 19 levels. These compel
 ling findings underscore the efficacy of our proposed technique in signifi
 cantly enhancing critical PPA metrics. The Hybrid Clock Network technique 
 represents a breakthrough in addressing the challenges of contemporary chi
 p design, offering a promising path forward in the pursuit of high-perform
 ance systems.\n\nTopic: Back-End Design, Embedded Systems, Front-End Desig
 n, IP
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