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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST186@linklings.com
SUMMARY:Faster Timing Closure of Multiple Power Domains Based Designs with
  SMVA
DESCRIPTION:Engineering Track Poster\n\nRajnish GARG and Rohit Goel (STMic
 roelectronics)\n\nMulti-voltage SoC's with uncorrelated supplies are becom
 ing predominantly common with a lot of devices coming up in the market wit
 h low power requirements. Here, Non-timing critical blocks are designed at
  lower voltage (power saving) and High-performance blocks are designed at 
 higher voltage (desired performance). In such Low power SOC's, Timing Clos
 ure poses a bigger challenge with tight schedules and predictable results 
 before tape-out as timing signoff of the chip has to be done on multiple c
 orners and multiple modes (MCMM). Single voltage timing analysis is easier
 . But, with the multi-level supply voltage and dynamic scaling features, t
 he timing analysis complexity increases because timing signoff has to be d
 one additionally on cross-voltage paths, which are not guaranteed to be wo
 rst case timing at either voltage corner. Multi-voltage designs need exhau
 stive analysis of cross voltage domain paths to make sure all worst-case p
 aths are identified under all voltage combinations. With numerous operatin
 g PVT corners, timing analysis across corners becomes further challenging.
  Synopsys Primetime's based Simultaneous multi-voltage aware analysis (SMV
 A) was helpful to attain this, to do the analysis of all cross-domain path
 s under all voltage scenarios in a single run, without the need for margin
 ing that can add pessimism. This paper describes Primetime based SMVA meth
 odology for predictable and faster Timing Closure of Multiple Power Domain
 s Based Designs.\n\nTopic: Back-End Design, Embedded Systems, Front-End De
 sign, IP
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