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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST189@linklings.com
SUMMARY:Redefining Hierarchical Power Integrity signoff for Ultra-Large Sy
 stem-on-Chips
DESCRIPTION:Engineering Track Poster\n\nPiyush Jain, Rossana Liu, Hailang 
 Wang, Apurva Soni, Medha Kulkarni, and Pranav Ranganathan (Microsoft) and 
 Chidambaram Rakkappan, Amit Jangra, Godwin Rajasekhar, and Sreekanth Rajan
  (Ansys)\n\nModern SoCs, with billions of transistors, pose challenges for
  traditional power integrity signoff due to increased node counts and proc
 ess scaling. The existing methods are time-consuming, require substantial 
 resources, and often result in systematic inaccuracies. To address this, a
  bottom-up hierarchical signoff methodology is proposed, which allows bloc
 k-level signoff and reduces the overall turnaround time without compromisi
 ng accuracy. This approach leverages the RedHawk-SC tool by Ansys to creat
 e child block models that are instantiated at the next hierarchical level.
  The hierarchical modeling flow has shown a performance improvement of ~45
 -50% during block level runs, with an accuracy within a 5% range compared 
 to flat runs. The methodology is under continuous improvement to enhance a
 ccuracy and efficiency. The next step involves implementing a Hierarchical
  SignalEM methodology using the same reduced model solution.\n\nTopic: Bac
 k-End Design, Embedded Systems, Front-End Design, IP
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