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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST192@linklings.com
SUMMARY:A Closed Loop IR and Timing Comprehensive Co-Signoff Methodology
DESCRIPTION:Engineering Track Poster\n\nOnkar Hule, Rossana Liu, Medha Kul
 karni, Hailang Wang, Amit Garg, and Pranav Ranganathan (Microsoft) and Sre
 ekanth Rajan and Amit Jangra (Ansys)\n\nTraditionally, the budgeting of ST
 A and IR drop limits was done separately, with each converging to their re
 spective limits without much interaction. Recently, there have been attemp
 ts to incorporate IR drop into STA analysis for a more informed timing sig
 noff. However, the reverse - incorporating timing critical path into IR si
 gnoff - has not been as thoroughly investigated.\nThis work proposed a met
 hodology for IR drop signoff with awareness of timing critical paths. It u
 tilizes the latest features from the Redhawk-SC EDA tool to incorporate ti
 ming analysis results into IR voltage drop signoff. This IR voltage drop d
 ata can subsequently be incorporated into an incremental timing analysis t
 o pinpoint potential waivers for IR violations. Evaluation data from real 
 design blocks in advanced nodes demonstrate that it can improve design cov
 erage and enhance silicon robustness and system performance.\n\nTopic: Bac
 k-End Design, Embedded Systems, Front-End Design, IP
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