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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST195@linklings.com
SUMMARY:An Integrated Behavioral Modeling Method for Mixed Signal IPs
DESCRIPTION:Engineering Track Poster\n\nBhupendra Singh, Rahul Kumar, Pall
 av Kumar, Jean-Aranud Francois, Mitu Mittal, and Anil Dwivedi (STMicroelec
 tronics)\n\nThe shrinking technologies have paved the path for complex dev
 ices having various functionalities integrating various IPs in a single So
 C and hence, complex clocking structure and efficient power management in 
 AMS IP are gaining popularity.  The same design complexity is reflected in
  HDL behavior model like timing from internal clock, real modeling, power 
 aware modeling etc. There is need of robust behavior modeling of these com
 plex IPs, to enable accurate and efficient functional check along with tim
 ing.\nIn this paper, the challenges and shortcomings associated with model
 ing of complex AMS IPs for timing simulations are discussed, along with th
 e proposed methodology. It has also been demonstrated how this methodology
  handles the correct data latching issue in case of negative timing checks
  present in the design, without compromising on any advanced feature suppo
 rted in the model.\n\nTopic: Back-End Design, Embedded Systems, Front-End 
 Design, IP
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