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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess232_ETPOST197@linklings.com
SUMMARY:Empowering Early-Stage Design: An Automated Solution for Die Size 
 Estimation and IO Ring Creation
DESCRIPTION:Engineering Track Poster\n\nGaurav Varshney (Texas Instruments
 ) and Dheeraj HA, Megha Naik, and MuraliMohan Thota (Texas Instruments (In
 dia) Pvt. Ltd.)\n\nIn the dynamic landscape of electronics design, the esc
 alating market demand for new devices has led to increased complexity in e
 valuating and comparing configurations and feature requirements based on c
 ustomer needs and packages. This intricacy poses a challenge for designers
 , making decision-making in this domain a laborious task. In the initial s
 tages of product development, designers' endeavor to assess the cost of th
 e new device by estimating its die size (silicon area) and exploring vario
 us configuration possibilities. Furthermore, a strategic focus on optimizi
 ng PPA (Power, Performance, and Area) at a given process node involves inc
 reasing performance (MHz) and adding memories, leading to higher power con
 sumption and larger die sizes. Ensuring compatibility with a target packag
 e (E.g., QFP: Quad Flat Package) introduces complexities like complex grou
 nd rings and down-bondings. Addressing these challenges necessitates highl
 y efficient, predictable, and fast solutions. Presently, there is a lack o
 f automated tools to tackle this problem. In this paper, we propose an aut
 omated solution to address aforementioned challenges, facilitating informe
 d decisions at the outset of the design process. This work aims to prevent
  late surprises and enhance overall predictability.\n\nTopic: Back-End Des
 ign, Embedded Systems, Front-End Design, IP
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