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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST198@linklings.com
SUMMARY:Accelerating Automated Custom Layout Creation Through Smart Design
  Intent Migration
DESCRIPTION:Engineering Track Poster\n\nGirish Vaidyanathan and Sravasti N
 air (Cadence Design Systems, Inc.)\n\nWith the semiconductor industry's pu
 sh to newer process nodes and shorter time to market, analog and custom IC
  layout creation is turning out to be the bottleneck as it has historicall
 y been a highly manual process. Since Analog IPs often stay the same acros
 s nodes, the ability to automatically recreate the designs can reduce cost
 ly iterations and help designs converge faster.\n\nWhen the design methodo
 logy requirements vary across process nodes, layout porting based on mappi
 ng of objects and scaling of sizes and coordinates fails miserably in prod
 ucing high-quality layout that is design rule correct. Our innovative appr
 oach of auto-inferring design intents from source layout and driving autom
 ated layout creation in target node solves the layout migration challenge 
 with upwards of 2X boost in productivity.\n\nThe schematics on the target 
 node are generated by mapping devices and parameters from the source schem
 atic and optimizing them for the target node using customizable machine le
 arning (ML)-based engines. Schematic-driven layout generates node and desi
 gn-specific grids to ensure DRC-correct placement and routing, while the m
 igration functionality seeds the target layout with relative placement inf
 ormation from the source layout including device groups, captured as scala
 ble templates, that take updated parameters and instance counts into accou
 nt. Incremental placer legalizes the placement followed by guard ring and 
 fill cell generation that are specific to target process node. In the last
  step, routing topology information from the source layout is used to gene
 rate routing in the target layout to help meet electrical and parasitic re
 quirements through a combination of automation and migration. The final LV
 S and DRC-clean layout on the target node is generated in a significantly 
 shorter time compared to manual creation, boosted by the use of existing l
 ayout footprint and patterns.\n\nTopic: Back-End Design, Embedded Systems,
  Front-End Design, IP
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