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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST201@linklings.com
SUMMARY:Design Enablement of 2D/3D Power-Thermal Self-Consistent Analysis
DESCRIPTION:Engineering Track Poster\n\nMohamed Naeim and Yun Dai (Cadence
  Design Systems, Inc.) and Dwaipayan Biswas and Dragomir Milojevic (imec)\
 n\nIn the last years, CMOS scaling becomes slower than used to be and it b
 ecomes more challenging to follow Moore's law. One of the proposed scaling
  boosters is system level 3D-IC where the vertical dimension is used by st
 acking dies on top of each other. Fine-pitch 3D interconnects such as wafe
 r-to-wafer hybrid bonding (10-1 ”m) leverage the benefits of 3D-IC by redu
 cing the wire length connections, hence improving PPA compared to the 2D c
 ounterparts. \nThermal hotspots become more challenging with 3D-IC for two
  reasons. First, reducing die footprint in 3D stacks leads to increasing t
 he power density. Second, bringing two dies in close proximity leads to he
 at confinement and poor heat dissipation. \nIn this work, a thorough 3D th
 ermal analysis is performed on MemPool design. Face-to-face 3D stack of Me
 mPool design leads to maximum temperature increase by 30șC compared to the
  2D counterpart configuration under static power conditions. Increasing te
 mperature escalates the static leakage power and resistance and results in
  total grid resistance and max IR-drop value to rise by 2.8% and 4.7% resp
 ectively.  \nCadence Celsius thermal solver and Voltus™ IC power integrity
  are used in the electrical-thermal co-simulation presented in this work.\
 n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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