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DTSTAMP:20240626T180035Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST203@linklings.com
SUMMARY:The Designer's Superpower! Early Circuit Verification with Calibre
  nmLVS Recon
DESCRIPTION:Engineering Track Poster\n\nKesmat Shahin (Siemens); Rahul Sai
  T Govindaswamy (Google); Smitha Shivaji Kamathi and Anish Padhi (Siemens)
 ; Rakesh Reddy, Karishma Qureshi, and Rajashekar Sura (Google); and Gurpre
 et Singh Lamba (Siemens)\n\nIncreasing complexity in integrated circuits (
 ICs) node over node results significant growth in circuit verification tim
 e and effort. Today's tapeout sensitivities make it critical to begin chec
 king and fixing connectivity issues in earlier design stages, since connec
 tivity violations will affect downstream flows such as reliability verific
 ation (PERC/ESD-checks), electromigration/voltage drop (EMIR) layout optim
 ization. However, running signoff verification in early stages typically p
 roduces thousands, if not millions, of layout errors, only some of which a
 re actionable. Addressing all these errors is an unproductive drain on bot
 h time and resources, as many will simply disappear when full-chip design 
 comes together at signoff, while finding and debugging relevant errors req
 uires a significant number of iterations and many manual steps. Critical p
 ain points in early design stage circuit verification include short isolat
 ion (SI), electrical rule checking (ERC), and soft connection checking (So
 ftchk). The Calibre nmLVS Recon tool is specifically designed to improve e
 arly-stage layout vs. schematic (LVS) verification providing targeted func
 tionalities to address these issues. Earlier focused circuit verification 
 reduces overall IC design verification and debugging time while improving 
 design quality and time to market, without compromising the signoff qualit
 y. Real-world results demonstrate the effectiveness and efficiency of the 
 Calibre nmLVS Recon tool.\n\nTopic: Back-End Design, Embedded Systems, Fro
 nt-End Design, IP
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