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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST204@linklings.com
SUMMARY:Overcoming the Growing Challenge of IR Drop by Effective Power Gri
 d Enhancement during Chip Finishing
DESCRIPTION:Engineering Track Poster\n\nRahul Sai T Govindaswamy (Google);
  Smitha Shivaji Kamathi and Ben Allen (Siemens); Ravikanth Kosuru and Prat
 eek Pendyala (Google); and Zvart Askanazyan, Christian Miles, Heba Sharaf,
  Esraa Swilliam, Jeff Wilson, and Gurpreet Lamba (Siemens)\n\nIntegrated c
 ircuit (IC) Power management is a growing challenge for both designers and
  manufacturers at advanced process nodes. We introduce an analysis-based s
 olution during chipfinishing flow. This innovative solution provides autom
 ated DRC-clean layout modifications that reduce IR drop without negatively
  impacting performance and area.\n\nKey metrics for a PnR flow focus on de
 sign performance, power, and area (PPA) goals. Using the solution, designe
 rs first analyze a chip for EMIR hotspots, then apply automated layout mod
 ifications to reduce resistance in these specific areas. These Correct-by-
 Construction modifications are based on a thorough understanding of availa
 ble routing tracks and signoff DRC rules, significantly reducing costly de
 sign iterations between PnR tools and the final physical verification solu
 tion.\n\nIn this presentation, We demonstrate integration of the collabora
 tive development of a Calibre DesignEnhancer tool into our design flow wit
 h Siemens to showcase the before and after EMIR results for an advanced no
 de that shows 30% reduction in IR drop. This reduces the iterations requir
 ed to correct the IR drop violations and eliminating iterations between Pn
 R and physical verification, the DRC-clean results provided by the Calibre
  DesignEnhancer tool that significantly reduce the time pressure of final 
 design closure while enhancing design quality of results for EMIR improvem
 ent.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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