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DTSTART:19700308T020000
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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST207@linklings.com
SUMMARY:Efficient HBM Channel Design in 2.5D Silicon Interposer with Signa
 l Integrity Optimization
DESCRIPTION:Engineering Track Poster\n\nFeng Ling and Yan Ma (Xpeedic)\n\n
 High Bandwidth Memory (HBM) in 2.5D interposers is to address the need for
  increased memory bandwidth in AI and HPC applications. HBM channel design
  is crucial for achieving the high-speed data transfers. However, routing 
 such a channel is challenging due to the tight interconnections and the ne
 ed to manage signal integrity (SI) in a compact space. It is common to tak
 e months to route a HBM channel and run multiple iterations to meet the SI
  requirement. The paper proposes an efficient flow including steps to quic
 kly explore routing pattern during the pre-layout stage with Xpeedic Metis
  tool, auto route the HBM channel with Synopsys 3DIC Compiler, and run pos
 t-layout SI analysis with integrated Xpeedic Metis. The demo example shows
  tremendous time saving with the new flow.\n\nTopic: Back-End Design, Embe
 dded Systems, Front-End Design, IP
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