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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
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UID:dac_DAC 2024_sess232_ETPOST217@linklings.com
SUMMARY:Struct Based Lower Level Modelling Using SystemVerilog UDT for Ver
 ification of Power Management IC
DESCRIPTION:Engineering Track Poster\n\nVijay Kumar, Keerthana K, and Cele
 ste Anil Lagali (Samsung)\n\nIn this presentation, we introduce typical ch
 allenges encountered in the Digital Mixed-Signal (DMS) verification of a P
 ower Management Integrated Circuit (PMIC), when its blocks are modelled in
  real number using High-Level Modelling (HLM) methodology.  We talk about 
 the traditional approach for modelling the PMIC blocks using SystemVerilog
  (SV) realnet using HLM, and mention the limitations of this approach.  We
  propose a two faceted modelling methodology to overcome those limitations
 , viz., a) Creation of Lower Level Models (LLM) to account for more holist
 ic verification in order to cover performance verification aspects, and ab
 ility to perform randomization and coverage, and b) Adoption of SV EEnet, 
 a user-defined nettype in SV with ‘struct' datatype, with which we can mod
 el impedance dependent interaction between blocks.  We thus illustrate the
  benefits of this SV-UVM compatible approach by showing how we could expan
 d on the DMS verification checklist, thereby performing fully comprehensiv
 e functional and performance verification of the PMIC.\n\nTopic: Back-End 
 Design, Embedded Systems, Front-End Design, IP
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