BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST218@linklings.com
SUMMARY:Memory Interface Architectures for Test Time Reduction in Zero DPP
 M SoCs
DESCRIPTION:Engineering Track Poster\n\nNitesh Mishra and Hrithik Sahni (T
 exas Instruments)\n\nThe semiconductor manufacturing process is far from p
 erfect; therefore, testing is required to distinguish between functionally
  correct devices and devices that are defective due to production abnormal
 ities. As the number of transistors on a die increases and more dies are a
 dded onto a board or into a package, it takes more time to test these devi
 ces. This, in turn, adds to the overall cost. Test time reduction is a cri
 tical step to reduce the overall cost of the device. On-chip memories have
  dominant footprint in today's SoCs. One of the SoCs with 650K flip flops 
 shows that memories contribute to around 50% of total chip area. Memory te
 sts are categorized into Memory Built-In Self-Test (MBIST) for internal me
 mory defect detection and Ram Sequential ATPG for at-speed detection of fa
 ults around the memories. Test time for RAMs and ROMs is driven by the num
 ber of memories that get tested in parallel, which depends on the power gr
 id budget of the SoCs. Multiple memories tested in parallel can increase t
 he peak power dissipation, potentially generating excessive heat and causi
 ng device damage. The key challenge in generating good quality RAM sequent
 ial patterns with high test coverage and optimized test pattern count for 
 memory dominated designs is degradation in the controllability on the memo
 ry inputs causing pattern inflation.\n\nTopic: Back-End Design, Embedded S
 ystems, Front-End Design, IP
END:VEVENT
END:VCALENDAR