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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST219@linklings.com
SUMMARY:Solving Memory Subsystem Verification Challenges for Multi-Instanc
 e Designs
DESCRIPTION:Engineering Track Poster\n\nShyam Sharma and Manish Chand (Cad
 ence Design Systems, Inc.)\n\nThis paper talks about the importance of the
  higher memory sub system level verification needs for protocol compliance
  of recent generation of memory sub systems using DDR like DDR5, Lpddr5 an
 d how Cadence verification IP memory model team has come up/implemented a 
 generic solution to describe such interconnect hierarchy in a modular and 
 simple way. This approach defines a feature, associated grammar to capture
  memory sub system and implementation of handshake mechanism with triggers
  (like commands) to enhance individual instance DRAM model to be able to g
 et visibility into other DRAM devices present in the design that are shari
 ng resources like data bus, ZQ registers etc. Paper also given example of 
 how this innovative solution has been used by Cadence memory controller IP
  and other external customers to enhance their sub system level verificati
 on to the next level while verifying protocol compliance for JEDEC define 
 specification for multi-rank memory sub systems for DDR5 and Lpddr5 based 
 designs. This solution can also potentially be applied to any Verification
  IP models to higher level protocol compliance checking.\n\nTopic: Back-En
 d Design, Embedded Systems, Front-End Design, IP
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