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DTSTART:19700308T020000
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BEGIN:VEVENT
DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240624T170000
DTEND;TZID=America/Los_Angeles:20240624T180000
UID:dac_DAC 2024_sess232_ETPOST222@linklings.com
SUMMARY:Unified Waveform Analysis Platform for Tr.-Level Design Verificati
 on
DESCRIPTION:Engineering Track Poster\n\nChoi Wonwoo, Kwangsun Kim, Sungho 
 Park, Hyungjung Seo, Younsik Park, and Jungyun Choi (Samsung)\n\nThis pape
 r presents a software tool designed to streamline the transistor-level des
 ign verification process. The tool excels in managing and integrating mult
 iple waveform formats, such as Synopsys FSDB and Cadence TRN/VWDB, into a 
 unified platform. This integration enhances the verification process's acc
 uracy and speed. A Python-based API, along with a C++ hybrid approach, is 
 utilized for ease of waveform manipulation and analysis. This tool overcom
 es the limitations of traditional verification methods in complex logic ci
 rcuit designs, offering a more efficient and precise verification methodol
 ogy.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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