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DTSTAMP:20240626T180002Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233@linklings.com
SUMMARY:Tuesday Engineering Track Poster Reception
DESCRIPTION:Engineering Track Poster\n\nCritical corners selection for sta
 ndard cells LVF characterization using AI\n\nOn-chip variation (OCV) is a 
 significant factor affecting timing sign-off for digital designs at 20nm a
 nd below. At lower technology nodes, timing measurements such as propagati
 on delay, setup time, and hold time may change by 50%-100% due to statisti
 cal variation. In order to capture these variatio...\n\n\nAravind Radhakri
 shnan Nair (Infineon Technologies) and Ajay Kumar and Lars Kishchuk (Sieme
 ns)\n---------------------\nDashboard Model for Foundry Early Node Assessm
 ents using Synopsys Design.da\n\nWith the increasing complexity and size r
 eduction of System-on-Chips (SoCs), evaluating diverse design rules become
 s crucial in early-stage Design-Technology Co-Optimization (DTCO) and init
 ial Performance, Power, and Area (PPA) assessments. \nIn response to these
  challenges, this paper presents a nov...\n\n\nLuna Kang, Jayson Seo, Ann-
 Woo Lee, and James Ban (Synopsys)\n---------------------\nDesign Methodolo
 gies for Minimizing Local Routing Congestions in Low-level Metal Layers\n\
 nIn advanced technology node, the difference in the ratio of cell height s
 caling and interconnect scaling has resulted in local routing congestion i
 n the low-level metal layers. This congestion is one of the bottleneck fac
 tors in node scaling. In this paper, we address two approaches to alleviat
 e the...\n\n\nDaeyeon Kim, HONGSEOK CHOI, Minkook Kim, and Sangyun Kim (Sa
 msung)\n---------------------\nAI-Enhanced Automated Optimization Workflow
  for HBM Interconnect on Interposer\n\nWith the rise of generative AI appl
 ications, there is a growing demand for high-bandwidth memory in AI/GPU ch
 ips, and interposer designs like UCIE for D2D and SOC to HBM interconnects
  are increasingly popular for chiplets interconnection. Interposer designs
  face unique challenges like small trace wi...\n\n\nShineng Ma, Hao Hu, Bi
 n Yu, and Keqing Ouyang (Sanechips Technology Co.,Ltd) and Rodger Luo (Ans
 ys)\n---------------------\nHigh Coverage QA for Process Variability Compe
 nsation in LVS Rule Deck\n\nManufacturing of semiconductor designs pass th
 rough many complex steps, among which is process variabilities compensatio
 n that is applied to the layout geometries as selective edge bias to impro
 ve the yield of the products. Biasing layout polygons will impact the resi
 stance and capacitances of the l...\n\n\nHeejae Lim, Jaeyoung So, Minho Ju
 ng, Jimin Yeo, Yunseong LEE, Bonhyuck Koo, and Yongseok Lee (Samsung) and 
 Ahmed Saleh and Mohamed Alimam (Siemens)\n---------------------\nGPU Accel
 erated Harmonic Balance SPICE Simulation\n\nHarmonic balance (HB) simulati
 on is a method to calculate frequency domain steady-state response in non-
 linear circuits. For multiple tones, high speed circuits in advanced Finfe
 t process, the runtime of HB analysis becomes particularly challenging. An
 d may often encounter convergence issues for lar...\n\n\nQikun Xue (NVIDIA
 ) and Chen Zhao (Empyrean Technology)\n---------------------\nAn effective
  Hierarchical Top Scope Signal EM Flow for closing Large SOC Designs\n\nTh
 is study introduces an innovative approach for closing large SOC designs e
 fficiently through an effective hierarchical EM flow. The methodology leve
 rages hierarchical analysis framework, integrating both top-level and bloc
 k-level EM considerations to address the complexities of large-scale SoC d
 es...\n\n\nAdish Mehta, Rakesh Reddy, and Umberto Garofano (Marvell) and R
 atnakar Bhatnagar and Steve Harvey (Cadence Design Systems, Inc.)\n-------
 --------------\nTowards a memory-address translation representation scheme
 \n\nVerification with application executables is common phase in virtual d
 evelopment kits (VDKs), RTL simulations and emulation. It involves both lo
 ading and dumping memory abstractions, usually modelled as 2D arrays, with
  the application hex images. This is usually acheived in 2 ways (i) frontd
 oor load...\n\n\nRathnakar Madhukar Yerraguntla (NXP Semiconductors)\n----
 -----------------\nResolving the seed promotion due to device layers deriv
 ation\n\nSeed promotion can be an issue during Hierarchical LVS leading to
  LVS incorrect results. The debugging methodology for finding the root cau
 se behind it involves a lot of trials. One of them being the way layers ar
 e derived using node-preserving layer operations. In this paper we show th
 e right metho...\n\n\nPrachi Mrudula and Atul Bhargava (STMicroelectronics
 ) and GAZAL SINGLA (Siemens)\n---------------------\nNavigating Instructio
 n Length Decode:  TAP into IP using three pronged FV Trident\n\nAmidst the
  increasing complexity of computing systems, the precision and integrity o
 f module designs, particularly the Instruction Length Decode unit (ILD) in
  modern processors, stand as paramount concerns. The ILD's role in identif
 ying instruction boundaries and enabling accurate field extraction b...\n\
 n\nVedprakash Mishra and Aarti Gupta (Intel Corporation)\n----------------
 -----\nEmpowering CDC analysis methodology with root cause analysis\n\nCDC
  static verification tool with machine learning (ML) capability helps engi
 neers with apt root cause analysis (RCA) to bring down the noise in result
 s. An improper constrained design may leak a bug into silicon, or an over 
 constrained design may not lead to verification closure. Often it is requi
 r...\n\n\nAbdul Moyeen and Manish Bhati (Siemens)\n---------------------\n
 Machine Learning Optimization Switch cells.\n\nPower gating design is esse
 ntial to save the power. It is important not only to design PDN (power del
 ivery Networks) but also to place switch cells in terms of number and dist
 ributions.\nIt is necessary of switch cell ratio as Design Methodology to 
 get robust power integrity by considering Static IR,...\n\n\nSungsu Byun (
 Samsung)\n---------------------\nFormal Tool Kit – A quick setup solution 
 for formal analysis\n\nFormal Verification is one of the major focus areas
  in the recent days to minimize project cycle times, faster coverage and e
 asy plug and use models. With the increase in computing power and formal t
 ools, the usage of formal in mainstream projects is increasing rapidly. Fo
 rmal verification setup is ...\n\n\nPhanindra Ramanujapuram and Rathnakar 
 Madhukar Yerraguntla (NXP Semiconductors)\n---------------------\nPowerdas
 h: A Comprehensive Framework for SOC Power Analysis and Tracking\n\nPowerd
 ash is an innovative push-button framework designed to serve as a holistic
  solution for System-on-Chip (SOC) power analyses. This framework offers a
  range of capabilities that enable SOC designers to efficiently analyze an
 d manage power-related data.\nPowerdash excels in delivering ultra-low la.
 ..\n\n\nVivek Joshi and Atman Kar (Texas Instruments)\n-------------------
 --\nChallenges Faced in Formal Based MSI: Tackle Formal Problem with a For
 mal Solution\n\nMetastability Injection (MSI) in the N-stage synchronisers
  for the synchronised paths, is the need essential to verify the robustnes
 s of the design against the uncertainties associated with the stability of
  synchroniser output. Although there are multiple ways to solve this, one 
 of them being Jasper...\n\n\nAbhinav Parashar and Ayush Jodh (Texas Instru
 ments (India) Pvt. Ltd.), Parthasarathy Ramesh (Texas Instruments), Harish
  Maruthiyodan (Texas Instruments (India) Pvt. Ltd.), and Gaurav Varshney (
 Texas Instruments)\n---------------------\nFuture Proofing Chiplet Testben
 ches: Resilience in Multiprotocol Era\n\nNow, chiplets aren't just any bui
 lding blocks; they're like the superheroes of the semiconductor world. By 
 promising the adaptability and scalability compels a need for a cost-effec
 tive and time-efficient approach to super architecture testing. Thus, dema
 nding sustainability of the overall design ve...\n\n\nKilaru Vamsikrishna,
  Anunay Bajaj, and Shaikh Salehabibi (Cadence Design Systems, Inc.)\n-----
 ----------------\nTiming Takedown Reports 3\n\nAs designs scale up in size
  and complexity timing takedown can become a tedious and overwhelming task
 . Gathering any insightful information from the millions of paths that are
  generated from a full timing run is, in many cases, not possible. The sol
 ution to this problem is generally scripts that rea...\n\n\nLukas Petterss
 on (Marvell)\n---------------------\nRDL and Bump Automation for Early EMI
 R Analysis In 2.5D, 3D and Single DIE Designs using RedHawk-SC Design ECO'
 s\n\nIn order to achieve the targeted PPA goals in our Single Die/2.5D/3DI
 C designs, accurate early analysis is crucial for IR and timing optimizati
 on from beginning stage of the project. \n\nIn the beginning of the projec
 t cycle:\n\n•        RDL with BUMPs is not available, Full flat design hie
 rarchy is not...\n\n\nArpan Bhowmik, Raja Rama Chandra Rao, Rishikanth Mek
 ala, and Goda Ananth Somayaji (Samsung)\n---------------------\nIntegrated
  Calculation of Capacitances for Image Sensor Arrays and other Periodic De
 signs\n\nAccurate coupling capacitances are a key part in the design of mo
 dern image sensor cells due to their high speed requirements, large number
  of active devices and interconnects, and complex inter-layer dielectric s
 tructure. Automation of 3D structure creation integrated with the design f
 low, as well ...\n\n\nValery Axelrad (SEQUOIA Design Systems. Inc.) and Og
 njen Milic (Independent)\n---------------------\nA Heuristic-Based Routing
  Methodology for Block-Level Memory Layout Routability Enhancement\n\nAs t
 he technology node shrinks, routing in memory devices is becoming a challe
 nging problem. Advanced commercial routing solutions have been introduced 
 for dealing with more complex design rules and less routing resources, how
 ever, routing results are still far from satisfactory. Complex routing pat
 ...\n\n\nSichan Kim and Seunghwan Lee (Samsung)\n---------------------\nMO
 DEL BASED SYSTEM  SEMICONDUCTOR ENGINEERING\n\nAbstract \n\nModel-based se
 miconductor engineering represents a paradigm shift in the design, develop
 ment, and manufacturing of semiconductor devices. This topic explores the 
 transformative impact of leveraging models at various stages from requirem
 ent to the real physical semiconductor design. Embrac...\n\n\nSmriti Joshi
  and Rosa Gragossian (Dassault Systèmes)\n---------------------\nAccelerat
 ing IO Liberty Generation through ML based Solution\n\nTime-to-market is a
  crucial factor in today's competitive chip design landscape. Accurate tim
 ing and power analysis are essential for successful tapeout, demanding fas
 t and precise Liberty characterization data (.libs). Traditional methods, 
 heavily reliant on SPICE simulations, are often time-consum...\n\n\nPawan 
 Verma, Anil-kumar Dwivedi, and Saurabh Srivastava (STMicroelectronics) and
  Ajay Kumar and Wei-Lii Tan (Siemens)\n---------------------\nSafeguarding
  datapath security requirements through formal verification\n\nIn the fast
 -evolving landscape of modern computing, where the exponential growth of d
 ata is ubiquitous, ensuring the confidentiality and integrity of informati
 on stands as a paramount challenge. This paper undertakes a comprehensive 
 exploration of data security, employing the lens of formal security...\n\n
 \nNicolae Tusinschi and Keerthi Devarajegowda (SEDA)\n--------------------
 -\nA Solution for Optimizing Customerized-MMB\n\nAs the proportion of memo
 ries increasing in design, MMB (Multi-Memory Bus) interface is widely used
  in HPC core for memory test, which is a predefined bus in Function RTL, p
 roviding an access to multiple memory arrays and no need for memory wrappe
 rs. As a result of MMB interface application, the tes...\n\n\nFeilong Pan,
  Minqiang Peng, Keqing Ouyang, and Guohua Zhou (Sanechips Technology Co.,L
 td) and Fengfeng Tang (Synopsys)\n---------------------\nFlash-based stora
 ge systems exploiting the data period for performance and security enhance
 ment\n\nWhen deleting data in the storage, the host system creates I/O req
 uests for the data and sends them to the storage. Besides, if the host sys
 tem sanitizes the data, it should also handle other I/O processes. Since t
 he deletion processes might burden the host system, the file system in the
  host system...\n\n\nJung-Hoon Kim, Suhwan Kim, and Daeun Oh (Samsung)\n--
 -------------------\nPhysical Design With Intelligence\n\nOptimizing chip 
 Power, Performance, Area, Schedule, and Cost (PPASC) is crucial to stay co
 mpetitive in today's rapidly evolving technological landscape. Optimal des
 ign PPASC, require designers to explore large design space of functional, 
 physical and process parameters that have complex relationship...\n\n\nBin
 du Rao, Jagadeesh Gnanasekaran, Prasenjit Ray, Sai Prashant, Anand Kumaras
 wamy, Srinivas Jammula, and Raj Dua (Intel Corporation)\n-----------------
 ----\nA module based automation for AXI performance monitoring, performanc
 e extraction and protocol checking.\n\nIn this paper we would like to prop
 ose an easy module bind based automation for the AXI protocol violation ch
 eck and extraction of the performance from any AXI-3 based bus. The automa
 tion infrastructure proposed, reduces the manual effort, time and human er
 ror in extracting the performance indices. ...\n\n\nNaveen Srivastava, Amr
 esh Lenka, and Sekhar Dangudubiyyam (Samsung)\n---------------------\nChal
 lenges and Improvements in StandardCell OpenAccess Content for Analog Desi
 gn\n\nDesigning an analog block involves more human intervention and exper
 tise compared to digital counterpart. Analog design flow is still strongly
  manual, which leads to a time-consuming and error-prone process. This pap
 er firstly reviews the difficulties faced by analog designers in handmade 
 schematic ...\n\n\nAnuradha Ray, Frederic Avellaneda, Stephan Weber, and A
 shish Kumar (STMicroelectronics)\n---------------------\nTapeout Data Pres
 ervation and automatic archival tagging for Optimal Disk Space Management\
 n\nDesign data management is an important concern from a chip design persp
 ective due to the enormous amount of data generated through the design flo
 w. This data, if not effectively managed can lead to disks running out of 
 space at critical times in a project, causing run crashes and increased tu
 rnaroun...\n\n\nYamini Ravishankar (Marvell)\n---------------------\nAn ef
 ficient QA methodology for SRAM libraries\n\nAt Renesas, we develop compac
 t and low-power SRAMs for our products. For our SRAM library development, 
 we produce and verify all 10,000+ memory instances generated by our Memory
  Compiler.  \n\nAll SRAM IPs must be validated across a wide range of proc
 ess, voltage, and temperature (PVT) conditions, as ...\n\n\nHiroaki Koizum
 i and Shuji Katayama (Renesas Electronics) and Siddharth Ravikumar and Mar
 y Rayburn (Siemens)\n---------------------\nPlug-n-Play Testbench environm
 ent for ARM Coresight SoC-400\n\nThe Coresight architecture is an integral
  part of any processor based design. ARM CoreSight architecture is a solut
 ion for debug and trace of complex SoCs. It provides a set of standard int
 erfaces and programmer model views enabling partners to define CoreSight c
 omponents and integrate them within t...\n\n\nSowmya V M, Dhaval Panchal, 
 Lalithraj Mailappa, Subramanian R, Naveen Srivastava, and Sekhar Dangudubi
 yyam (Samsung)\n---------------------\nAutomated Constraint Promotion Meth
 odology from IP to SoC for Complex Designs\n\nIP cores require integration
  into top-level subsystems and/or SoCs. Writing constraints manually for t
 op level design is prone to errors and difficult to verify and manage. Thi
 s Synopsys webinar will cover how automated SDC constraints promotion from
  the IP to SoC level provides high-quality SDC rel...\n\n\nMallik Devulapa
 lli and Rimpy Chugh (Synopsys)\n---------------------\nElevating BFM Capab
 ilities: seamless generation and validation of Proprietary Ethernet Frame 
 in the absence of Physical interface connections with RTL\n\nBus Functiona
 l Models (BFMs) are commonly used in digital design and verification proce
 sses. They serve as abstract representations of the behavior of buses or c
 ommunication interfaces within a system. People use BFMs for several reaso
 ns, such as early system-level simulation, verification of commun...\n\n\n
 Krunal Patel and Shubham Agarwal (Cadence Design Systems, Inc.)\n---------
 ------------\nAutonomous Power Sequence validation solution for I/O using 
 Solido Design Environment\n\nThe characterization of input/output (IO) dev
 ices is  complex and time-consuming process due to the multiple supplies i
 nvolved, such as VDD and VDDE, which ramp up at different rates and in dif
 ferent orders. This is particularly important in the context of modern com
 plex IO design, which often requi...\n\n\nravinder kumar (STMicroelectroni
 cs) and Fouad Mkalech, Eric Mammi, and Vani Priya (Siemens)\n-------------
 --------\nAdvancements in Source Synchronous Design Implementation: An EDA
  Perspective\n\nAs we move towards lower-technology nodes, the challenges 
 in design implementation intensify & enhancing design methodologies and al
 gorithms becomes crucial. By encouraging the integration of different stag
 es, we can significantly improve the implementation  process. We present a
 n innovative methodo...\n\n\nKeshavkumar Durgakeri, Subba Ramkumar Reddy A
 nnapalli, and Ponnada Naidu (Intel Corporation)\n---------------------\nA 
 PVT-robust Design with Electronic/Photonic Co-simulation Engine for Micror
 ing-based DWDM 3-D Silicon Photonics\n\nHewlett Packard Labs has been rese
 arching high-speed low-power dense wavelength division multiplexing (DWDM)
  Silicon Photonics (SiPh) system for post-exascale high-performance comput
 ing system. We propose a process/temperature/voltage (PVT) variation analy
 sis for SiPh designs leveraging electronic-p...\n\n\nChaerin Hong, Luca Ra
 mini, and Marco Fiorentino (Hewlett Packard Enterprise); Ahsan Alam and Ze
 qin Lu (Ansys); and Raymond Beausoleil (Hewlett Packard Enterprise)\n-----
 ----------------\nRisk Management in Volume Diagnostics\n\nWafer diagnosti
 cs plays the key role in enabling yield pull-in by providing critical data
  for yield improvement at foundry. The key deliverables are defect candida
 te data for failure analysis(FA) and wafer sort analysis. Foundry encounte
 rs issues with missing wafer data, delayed data, wrong/partial ...\n\n\nPi
 tchumani Guruswamy (Silicon Support Solutions (OPC) Private Limited) and V
 ishnu Raj (Independent)\n---------------------\nRow-Based Placement and Le
 galization for Mixed Signal Power Delivery IP in Memory\n\nThe turn-around
 -time for analog IP layout design significantly exceeds that for digital, 
 despite their low quantity. Although automated migration solutions for ana
 log IP have been proposed recently, their practical application is still c
 hallenging because even when the schematic is reused, layout re...\n\n\nJe
 ongyoon Lee, Kyeongrok Jo, Seunghwan Lee, Seungkwang Hong, Heejin Bae, Jiw
 on Woo, Youngwook Kim, and Jungyun Choi (Samsung)\n---------------------\n
 Next-Gen comprehensive IR analysis with Ansys SigmaAV\n\nIn advanced techn
 ology nodes, metal pitches have not scaled with area which has led to incr
 eased cross-coupling between instances where switching instances in the im
 mediate vicinity have a significant impact on an instance's IR drop, with 
 a measurable impact from areas outside the immediate vicinity...\n\n\nPran
 av Ranganathan, Medha Kulkarni, and Chip Stratakos (Microsoft) and Veshal 
 Sridhar and Mallik Vusirikala (Ansys)\n---------------------\nHeterogeneou
 s 3DIC  Multi Voltage Timing Signoff\n\nCross die paths in 3DIC requires m
 any additional signoff corner analysis compared to conventional 2DIC     s
 ignoff corners owing to different possible conditions at each die level. I
 n case of multi voltage 3DIC interface, signoff corners need to be coupled
  with 3DIC voltage scenarios in order to cre...\n\n\nTusharkant Mishra, Ra
 njith V R, and Damodaran Trikkadeeri (Samsung) and Santosh Varanasi (Synop
 sys)\n---------------------\nSolving the antenna debug challenge in physic
 al design verification\n\nDesign teams find it increasingly challenging to
  debug antenna violations, especially at\nadvanced nodes, due to increasin
 g complexity in antenna rules. Antenna rule checks may\ncontain multiple s
 cenarios with different conditional constructs, which make it difficult\nf
 or engineers not only to distingu...\n\n\nRahul Sai T Govindaswamy (Google
 ), Nermeen Hossam and Anish Padhi (Siemens), Karishma Qureshi (Google), Gu
 rpreet Lamba (Siemens), and Rakesh reddy Katukuri (Google)\n--------------
 -------\nDIGITAL CONTINUITY FROM SEMICONDUCTOR EBOM TO MBOM AND BILL OF PR
 OCESS\n\nAbstract :\n\nDigital continuity plays a crucial role in modern s
 emiconductor industry. Semiconductor design and manufacturing complexity i
 nclude the need for sophisticated process control, rigorous quality assura
 nce, and seamless integration with upstream and downstream operations. Thi
 s topic explore...\n\n\nSmriti Joshi and Manuel Rei (Dassault Systèmes)\n-
 --------------------\nA Novel Flow to Verify SoC Integration with Formal P
 roperty Verification\n\nFormal Verification is widely applied at IP level.
  FPV and its Apps are largely used (Linting, Register check, Coverage). IP
 s are often signed-off only with Formal. Our aim is to use FPV at SoC leve
 l.\n\nOur top-level verification tasks:\n\n1.        IP integration:\n    
       Check that all the IPs are ...\n\n\nDavid Vincenzoni and Marcello Du
 sini (STMicroelectronics)\n---------------------\nEarly detection of low p
 ower related issues using formal verification\n\nLow Power design is now r
 equired to satisfy the current global market request in reducing ASIC powe
 r consumption. Incorrect power aware description can compromise the origin
 al design functional behavior, such as the propagation of corrupted signal
 s due to an incorrect isolation control signals proto...\n\n\nAndrea Lopin
 to and Paola Baldrighi (STMicroelectronics)\n---------------------\nEnhanc
 ing and accelerating Verification with ad-hoc Python scripting\n\nThe obje
 ctive of this paper is to show how it is possible to enhance and accelerat
 e verification by exploiting Python scripting.\nDigital verification engin
 eers are very often required to write a huge amount of repetitive code. Th
 is is particularly evident for verification structures used to verify m...
 \n\n\nEdoardo Bollea and Davide Sanalitro (STMicroelectronics)\n----------
 -----------\nDevelopment of SystemC-based Security VP for In-House SED SSD
  Firmware Verification and Application of libFuzzer\n\nDue to difficulties
  in supporting Open Source Project in the Embedded System environment and 
 limitations in applying fuzzing technology, we used SystemC-based full-pat
 h SSD VP, but it was not easy to apply due to performance issues and many 
 unnecessary functions for SED verification. \n\nAccordingly, ...\n\n\nCHAN
 GWON KIM (Samsung)\n---------------------\nPeak Power Optimization using A
 ctive Datapath Operator Profiling\n\nPower estimation has become a critica
 l metric for design evaluation and thus the focus now is on both Average a
 nd Peak Power. Using strategies like Clock-Gating, to reduce the average p
 ower may also reduce peak power. With focus on average power, the strategi
 es which reduced peak power with no or mi...\n\n\nVijay Tayal, Sanchita Gu
 pta, Amit Dey, Anil Mishra, Hicham Anbar, Mohammad Saif Ansari, and Manish
  Kumar (Siemens)\n---------------------\nAn Efficient Early Thermal Manage
 ment Solution in 3DIC design\n\nMulti-die designs, 2.5DIC and 3DIC, have b
 een rising in popularity in last decade as they offer tremendously increas
 ed levels of integration, smaller footprint, performance gains, and more. 
 While they are attractive for many applications, it also creates more stri
 ngent design bottlenecks in the area...\n\n\nPing Ding, Guohua Zhou, and K
 eqing Ouyang (Sanechips Technology Co.,Ltd) and Li Zou and Shuqiang Zhang 
 (Ansys)\n---------------------\nAn uptick on Automotive Safety Solutions u
 sing Cadence Implementation Tools\n\nAn explosion in automotive applicatio
 ns in the form of driverless cars, complex space explorations, aviation ad
 vancements has made it mandatory for the Design and EDA community to come 
 up with solutions focused on the safety of such devices. There have been e
 arlier attempts to explore safety-based f...\n\n\nJitendra Jain and Ashwin
  Ramamurthy (Cadence Design Systems, Inc.)\n---------------------\nAn Auto
 mated Solution for Streamlining Qualifications of Connectivity and DRC Acr
 oss Diverse 3DIC Packaging Technologies\n\nThe integration of multiple die
 s and substrates into a unified 3D-IC package presents a compelling soluti
 on to the limitations posed by scaling and challenges in SOC migration, ma
 king it a focal point in semiconductor advancement. Despite its prominence
 , diverse fabrication methodologies, teams, and...\n\n\nTaehyung Lee, Woon
 ggyu Lee, Minkyung Kim, Jihoon Park, Hyojin Kim, Changyoon Shin, Jiseon Le
 e, Yoojeong Yang, Seungjae Jung, and Jongkoo kang (Samsung) and Ahmed Sale
 h (Siemens)\n---------------------\nArchitecture Area Evaluation Tool\n\nA
 AET (Architecture Area Evaluation Tool) is designed to address the pressin
 g need for accurate and unified area estimation for future devices. A prec
 ise estimation plays an important role in determining the approximate cost
  of the devices in terms of area so as to meet the market requirements.\n\
 nAAET...\n\n\nAshishkumar Pal and Adarsh TR (Texas Instruments (India) Pvt
 . Ltd.) and Kavithaa Rajagopalan (Eindhoven University of Technology)\n---
 ------------------\nNovel Preprocessing Technique for Data Embedding in En
 gineering Code Generation Using Large Language Models\n\nIn engineering, t
 he use of Large Language Models (LLMs) for specific domain code generation
  presents a significant challenge and an important area of study. These mo
 dels are crucial in assisting programming and development tasks, but they 
 often require substantial computational resources and extensi...\n\n\nYu-C
 hen Lin (National Taiwan University); Akhilesh Kumar, Norman Chang, Wen-li
 ang Zhang, and Muhammad Zakir (Ansys); and Jyh-Shing Jang (National Taiwan
  University)\n---------------------\nMatched Placement and Routing using S
 ynchronized Unit Cell Array\n\nIn Analog Design, matching is very critical
  to ensure yield, as even a few millivolts difference between neighboring 
 devices can break the circuit. In this paper, we present a flow for matche
 d placement and routing using Group Arrays. Group Arrays are repeated patt
 ern of synchronized unit cells. The...\n\n\nPriyanka Madaan (NXP Semicondu
 ctors); Akshita Bansal and Ashwani sanwal (Cadence Design Systems, Inc.); 
 and Avinash Tripathi (NXP Semiconductors)\n---------------------\nAvoiding
  CDC bugs introduced during Synthesis Optimizations and Netlist Transforma
 tions\n\nDesign synthesis flows are not aware of Clock Domain Crossing (CD
 C). Thus, synthesis optimizations that are built to enhance power, perform
 ance, and area (PPA), may cause corruption in CDC paths and therefore, the
  netlist generated by the synthesis tools can introduce new CDC errors eve
 n after CDC s...\n\n\nsuresh barla and PARAS MAL JAIN (Synopsys), harish A
 epala and anshul bansal (Meta), and Gunjan Mamania and Kenneth Trejos (Syn
 opsys)\n---------------------\nMachine Learning-based feasibility estimati
 on of digital blocks for improved productivity in Analog-on-Top Back-End d
 esign flows\n\nAnalog-on-Top Analog Mixed Signal (AMS) Integrated Circuit 
 (IC) design is a time-consuming process predominantly carried out by hand.
  Within this flow, usually, some area is reserved by the top-level integra
 tor for the placement of digital blocks. Specific features of the area, su
 ch as size and shap...\n\n\nGabriele Faraone, Eugenio Serianni, Dario Lica
 stro, Nicola DiCarolo, Michelangelo Grosso, and Giovanna Franchino (STMicr
 oelectronics)\n---------------------\nAsk-EDA: A conversational agent for 
 tools, methodology, technology and design problems\n\nLarge language model
 s (LLMs), like ChatGPT, has been shown to be quite effective at providing 
 information retrieval.  By leveraging conversational AI, we have extended 
 the functionality of the our in-house stack overflow-like system. We provi
 de a virtual assistant capable of answering questions abou...\n\n\nMichael
  Kazda, Bradley Sears, and Nicholas Shropshire (IBM) and Luyao Shi (IBM Re
 search)\n---------------------\nSSN and EMA Bus Path Automation\n\nAs desi
 gns grow larger and more complex, more advanced Design for Test (DFT) appr
 oaches continue to be developed to keep up with the capacity required. One
  of these approaches is "Streaming Scan Network" (SSN), which is aimed at 
 distributing scan test data across the entire design through a bus stru...
 \n\n\nGreg Ford and Trinath Harikrishna (Marvell)\n---------------------\n
 A Novel Automation flow to generate SV-UVM Testbench with integrated BFMs\
 n\nThe design verification (DV) phase in chip production lifecycle is a cr
 ucial and time-consuming process.\nFor any new IP/SoC, creating a DV envir
 onment from scratch is time consuming, repetitive and cumbersome task. Thi
 s usually requires 2-3 weeks of effort from DV Engineer. Furthermore, if t
 hird par...\n\n\nParthasarathy Ramesh, Sagar Jogur, Raminder Kaur, and Atu
 l Lele (Texas Instruments)\n---------------------\nTrue-Hybrid SaaS Cloud 
 Architectures for EDA Workloads\n\nModern chip development craves the clou
 d's immense power, but on-premises dependencies hold back a complete migra
 tion. This presentation introduces the "True Hybrid" workload model, where
  design emulation remains on-premises while simulation/verification soars 
 in the cloud. Our approach tackles key ...\n\n\nRavi Poddar (Amazon Web Se
 rvices) and Amit Varde and Nupur Bhonge (Keysight Technologies)\n---------
 ------------\nAccelerated Design Rule Learning for Silicon Photonics\n\nTh
 e amount of data generated in 2025 is estimated to be 181 zettabytes (181,
 000,000,000,000,000,000,000 bytes). To accommodate this, the size of data 
 centers keeps expanding, putting different servers of the same data center
  several miles away from each other. Optical fibers are a necessity betwee
 n ...\n\n\nApoorva Vakil, Romain Feuillette, and Timothy Miller (GlobalFou
 ndries)\n---------------------\nEnhancing Analog Mixed-Signal (AMS) Verifi
 cation:  Advanced Methods for Runtime and Scope Optimization\n\nThis paper
  presents innovative approaches to reduce the runtime of complex System on
  Chip (SoC) verification, particularly in the context of Analog Mixed-Sign
 al (AMS) co-simulation. The methodologies discussed can be applied to impr
 ove the scope of AMS simulations and improve the quality and coverag...\n\
 n\nAadhar Sharma, Avinash Chaudhary, Sooraj Sekhar, and Lakshmanan Balasub
 ramanian (Texas Instruments (India) Pvt. Ltd.) and Gaurav Varshney (Texas 
 Instruments)\n---------------------\nVirtual Instrumentation Based Predict
 ive Checks for Shift-Left Low Power Verification\n\nSynopsys VC LP is a st
 atic low power verification checker which helps to verify consistency betw
 een UPF and design throughout the design flow. \nTraditional use models of
  VC LP allow to make sure UPF is correct and complete at RTL stage and at 
 netlist stage, the low power cells (multi-voltage or MV c...\n\n\nSachin B
 ansal, Yi Liu, Vijay Poosa, M.Vaishnavi Reddy, Nupur Gupta, Vishal Keswani
 , Amit Goldie, and Manish Goel (Synopsys)\n---------------------\nDVD-awar
 e STA and its silicon correlation results on 10nm test chip\n\nAs technolo
 gy scales down, metal resistances have increased, resulting in potentially
  more voltage drop. Therefore, Dynamic Voltage Drop (DVD) significantly af
 fects performance in recent process technologies. Moreover, transistor den
 sity has increased, resulting in higher power density. Thus, power ...\n\n
 \nJongyoon Jung, Hyun-seung Seo, and Byunghyun Lee (Samsung) and Rajat Kuk
 reja, Ajay Sahoo, Ji-Hun Kim, Dae-Hun Jung, and Aniket Deshmukh (Cadence D
 esign Systems, Inc.)\n---------------------\nScalable modeling of dynamic 
 voltage compression on timing\n\nOn leading node designs, we see power sup
 ply integrity becoming more important and meeting the dynamic compression 
 requirement becomes more difficult.  We can use various techniques to fix 
 local hotspots, but these techniques can be time consuming and iterative. 
  Analyzing the power supply effect on...\n\n\nTim Helvey (Marvell)\n------
 ---------------\nWatsonX and DDB for AI Based Design Analytics and Visuali
 zation\n\nIn this presentation,  we are very pleased to introduce synergy 
 between watsonx.ai and the Design Data Browser (DDB for short).  DDB is po
 werful high-performance X-windows based application which serves as a cent
 ral cockpit uniting our core timing and physical database, known as DD, as
  well as our w...\n\n\nKerim Kalafala, Nathaniel Hieter, and Douglas Kelle
 r (IBM)\n---------------------\nNew SoC Creation Flow based on Extraction 
 and recreating from previous SoC\n\nSoC creation is done by integrating Lo
 gical subsystems using system verilog language. Connectivity between diffe
 rent subsystems is defined by different specs. Some specs are defined in D
 ocuments and xls formats which leads to a real challenge to keep Design up
  to date with developing spec. When movi...\n\n\nMaël Rabé and Chouki Akto
 uf (Defacto Technologies)\n---------------------\nA New Approach to Effici
 ent Prelim Package Generation for Faster SOC Implementation\n\nIn the fast
 -paced semiconductor world, rapid time-to-market is crucial. Traditional S
 oC development, waiting for fully developed IPs, hinders speed and competi
 tiveness. This presentation introduces the concept of preliminary IP CAD v
 iews, generated as soon as IP specifications are defined. This allo...\n\n
 \nBhupendra Singh, Shoikat Das, Saurabh Srivastava, and Anil Dwivedi (STMi
 croelectronics)\n---------------------\nEarly Validation of Random TB usin
 g Formal Technology\n\nFunctional Coverage serves as a metric for measurin
 g the completeness of verification efforts, often requiring a significant 
 time investment. The testbench (TB) employed to achieve verification cover
 age may involve complex constraints and incomplete scenarios, potentially 
 causing issues of over-cons...\n\n\nEuibong Jung (Samsung)\n--------------
 -------\nA Data-Driven Automation Method of Liberty Model Characterization
  for Custom Cells\n\nVarious custom cells are used in DRAM and NAND Flash 
 memories to optimize power, performance, and area. Liberty model character
 ization of the custom cells becomes a time-consuming manual task when an a
 utomation tool is unable to extract the timing arc and Spice input decks, 
 called configuration for ...\n\n\nDongsub Yoon, Youngjin Ju, and Hyojin Ch
 oi (Samsung)\n---------------------\nAnalysis of Rare Failure Events: An I
 mproved Scaled-Sigma Sampling Method\n\nHigh sigma analysis is an importan
 t topic in circuit design and analysis area, which predicts the probabilit
 y of rare circuit/device failure events in VLSI circuits, such as in SRAM 
 arrays. There are EDA start-ups specifically dedicated to address rare fai
 lure event problems, such as Solido, MunEDA,...\n\n\nNing Lu (IBM)\n------
 ---------------\nAdvanced Static Methodology for Complete Connectivity and
  Glitch Signoff\n\nA chip design consists of interconnected blocks providi
 ng advanced functionality. While these blocks are thoroughly verified, the
  integrity of connections between these pre-verified components lacks clea
 r ownership and efficient verification processes. With growing design comp
 lexity, the number of s...\n\n\nAbhishek Ghate (HCL Technologies) and Saur
 av Choudhary and Vikas Sachdeva (Real Intent)\n---------------------\nCove
 rage-based FV signoff – The complete cleanup methodology\n\nFormal-Verific
 ation (FV) is aiming to become a mainstream validation flow. For that, a s
 ignoff methodology is needed in the same way there is for dynamic validati
 on. The main potential issues in FV are: overconstraint by assumptions, an
 d assertions that don't cover the whole design. FV tools are abl...\n\n\nG
 ilboa Alin, Daher Kaiss, Anmol Patel, Aarti Gupta, and Gavriel Gavrielov (
 Intel Corporation)\n---------------------\nImplementing World's First Full
 y Integrated SoC Solution For Direct-To-Satellite IoT Connectivity\n\nThis
  paper explores some of the challenges encountered during the digital impl
 ementation of the world's first fully integrated SoC solution for Direct-t
 o-Satellite IoT connectivity chip. The chip is a mix of analog and digital
  sections and was implemented in GF 22nm process node. Due to the stringen
 ...\n\n\nSushanta Sarmah (Orca Radio Systems Pvt Ltd) and Alpesh Kothari a
 nd Raghu Ram Gude (Siemens)\n---------------------\nLINKED LIST PROOF ACCE
 LERATOR\n\nLinked lists provide a flexible and efficient way to share reso
 urces across multiple queues. While implementing a linked list is straight
 forward, its verification poses complexities. Using traditional simulation
  techniques, finding and debugging can be challenging and time-consuming. 
 Formal verifica...\n\n\nArjun Kumar (Broadcom)\n---------------------\nAut
 o Grouping And Improvement Of IR Critical Regions Using Unsupervised Learn
 ing\n\nIn our 2.5D/3D System on Chip (SoC) designs that are being develope
 d at lower (< 10nm) technology nodes, it is crucial to ensure that the IR 
 drop is within the signoff threshold limits in order to achieve the target
 ed PPA goals. \n\nTraditionally this includes multiple iterations of IR si
 mulations aft...\n\n\nArpan Bhowmik, Abhishek Mahesh Chinchani, Rishikanth
  Mekala, and Goda Ananth Somayaji (Samsung)\n---------------------\nSimula
 tion and Measurement of MOMCAP Breakdown Risk Based on TCAD\n\nMetal-oxide
 -metal-capacitance(MOMCAP) is widely used in integrated circuits because o
 f its high unit capacitance, low parasitic, and good RF characteristics. A
 s MOMCAP is increasingly sensitive to manufacturability in advanced techno
 logy, the foundry typically provides design rules with large margin...\n\n
 \nKun Zhou, Jian Wang, Tingting Hun, Guohua Zhou, and Keqing Ouyang (Sanec
 hips Technology Co.,Ltd)\n\nTopic: Back-End Design, Embedded Systems, Fron
 t-End Design, IP
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END:VCALENDAR