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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST008@linklings.com
SUMMARY:A Novel Flow to Verify SoC Integration with Formal Property Verifi
 cation
DESCRIPTION:Engineering Track Poster\n\nDavid Vincenzoni and Marcello Dusi
 ni (STMicroelectronics)\n\nFormal Verification is widely applied at IP lev
 el. FPV and its Apps are largely used (Linting, Register check, Coverage).
  IPs are often signed-off only with Formal. Our aim is to use FPV at SoC l
 evel.\n\nOur top-level verification tasks:\n\n1.        IP integration:\n 
          Check that all the IPs are correctly connected on the bus and acc
 essible by the masters.\n\n2.        IP operation:\n          Check that a
 ll the IPs are functionally working in SoC.\n\n3.        System behavior:\
 n            Check that the main application is working.\n\nThe tests are 
 usually developed in C code and executed by a CPU in a UVM test bench.\n\n
 The paper is focused on step 1; the idea is to use the Formal Property Ver
 ification to prove the IP integration. Internally developed Python utility
  generates specific SVA assertions by a simple SoC description excel file.
  It produces read-write properties that check the accessibility of the per
 ipheral registers and memory spaces from the CPU bus master.\n\nThis appro
 ach verifies the SoC integration early in the flow, with no UVM; the bugs 
 commonly discovered are: \n-        Wrong memory map\n-        Wrong data 
 bus connection\n-        IP clock and/or reset stuck-at\n-        Wrong pe
 ripheral's reset value\n\nTopic: Back-End Design, Embedded Systems, Front-
 End Design, IP
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