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BEGIN:VEVENT
DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST022@linklings.com
SUMMARY:Enhancing and accelerating Verification with ad-hoc Python scripti
 ng
DESCRIPTION:Engineering Track Poster\n\nEdoardo Bollea and Davide Sanalitr
 o (STMicroelectronics)\n\nThe objective of this paper is to show how it is
  possible to enhance and accelerate verification by exploiting Python scri
 pting.\nDigital verification engineers are very often required to write a 
 huge amount of repetitive code. This is particularly evident for verificat
 ion structures used to verify memory elements, such as register maps, OTPs
  or NVMs. The main risk related to this task is the likeliness of committi
 ng mistakes while writing the same thing, slightly changed, over and over.
  Moreover, small changes in specification may lead to a large amount of co
 de to be rewritten.\nThe solution found lies in a proficient use of the Py
 thon language to analyze and elaborate specification files to produce all 
 the code needed for verification, both UVM and Formal.\nTwo cases are pres
 ented: the first one is a specific application for register maps. The seco
 nd use case is a generic approach to covergroups and assertions writing au
 tomation.\nResults can be summarized as follows: it was found that both th
 e initial time and maintenance time are reduced across the duration of a s
 ingle project. Additionally, by sharing the scripts among different team m
 embers, the script writing effort becomes neglectable. Lastly, having your
  own scripts allows you to customize them to your own needs.\nOverall, the
  usage and reusage of python scripts reduces verification time, leading to
  a shorter time-to-market.\n\nTopic: Back-End Design, Embedded Systems, Fr
 ont-End Design, IP
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