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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST026@linklings.com
SUMMARY:Early detection of low power related issues using formal verificat
 ion
DESCRIPTION:Engineering Track Poster\n\nAndrea Lopinto and Paola Baldrighi
  (STMicroelectronics)\n\nLow Power design is now required to satisfy the c
 urrent global market request in reducing ASIC power consumption. Incorrect
  power aware description can compromise the original design functional beh
 avior, such as the propagation of corrupted signals due to an incorrect is
 olation control signals protocol. Low Power structural checks ensure that 
 the design is structurally safe but do not guarantee functional correctnes
 s. Low Power functional simulations highly depend on simulation scenarios,
  which may result in non-exhaustive verification in case of a lack of test
  cases.\n\nThis paper details our experiences in establishing a robust pow
 er aware verification flow to catch low power Bugs early in the design cyc
 le reducing the overall sign-off time. We present how the power aware form
 al verification, combined with a custom automatic property's extraction, h
 elped us to obtain a simulation scenario independent analysis of power awa
 re design functionality. The flow allows fast and specific LP checks witho
 ut requiring any verification scenario setup. We share the results of our 
 analysis, which highlight the bugs found using this methodology. We shall 
 show how you can adopt this flow to make your power aware signoff comprehe
 nsive.\n\nTopic: Back-End Design, Embedded Systems, Front-End Design, IP
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