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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
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UID:dac_DAC 2024_sess233_ETPOST038@linklings.com
SUMMARY:Towards a memory-address translation representation scheme
DESCRIPTION:Engineering Track Poster\n\nRathnakar Madhukar Yerraguntla (NX
 P Semiconductors)\n\nVerification with application executables is common p
 hase in virtual development kits (VDKs), RTL simulations and emulation. It
  involves both loading and dumping memory abstractions, usually modelled a
 s 2D arrays, with the application hex images. This is usually acheived in 
 2 ways (i) frontdoor loading using design modules mimicking real silicon (
 ii) backdoor loading using external methods such as simulator API to initi
 alize the design in an "image-loaded" state. The former is slow and ineffi
 cient since the design spends a lot of time in loading process along with 
 additional design modules for support. The latter can be performed efficie
 ntly without additional design modules but requires a lot of platform-spec
 ific  infrasturcture with memory-dependent details (for ex: ECC, endiannes
 s, controller size). In this presentation we argue that a succint represen
 tation of such details is possible for most memories. Such a representatio
 n is possible because of stereotypical operations on the memory abstractio
 ns. We show that tools processing such representations dramatically reduce
  the maintainable code size.\n\nTopic: Back-End Design, Embedded Systems, 
 Front-End Design, IP
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