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DTSTAMP:20240626T180033Z
LOCATION:Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20240625T170000
DTEND;TZID=America/Los_Angeles:20240625T180000
UID:dac_DAC 2024_sess233_ETPOST039@linklings.com
SUMMARY:New SoC Creation Flow based on Extraction and recreating from prev
 ious SoC
DESCRIPTION:Engineering Track Poster\n\nMaël Rabé and Chouki Aktouf (Defac
 to Technologies)\n\nSoC creation is done by integrating Logical subsystems
  using system verilog language. Connectivity between different subsystems 
 is defined by different specs. Some specs are defined in Documents and xls
  formats which leads to a real challenge to keep Design up to date with de
 veloping spec. When moving from one SoC to another and rebuilding with sem
 i-automation, we face a multitude of major bugs. We understood that our cu
 rrent solution based on Verilog-auto features reached its limits.\n\nThrou
 gh the presented methodology, we build an automated process enabling to: E
 xtract connectivity information from an existing SoC project; Categorize t
 he extracted connectivity, to keep only what is required for the new gener
 ation of SoC projects; and Generate the new connectivity.\n\nDefacto custo
 mer built this methodology based on Defacto's SoC Compiler APIs which enab
 led us to generate a full top level in 5 seconds.\nWe estimate a global re
 duction of at least 40% of the execution and Man month overall effort.\n\n
 Topic: Back-End Design, Embedded Systems, Front-End Design, IP
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