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DTSTAMP:20240626T180034Z
LOCATION:Level 2 Exhibit Hall
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UID:dac_DAC 2024_sess233_ETPOST046@linklings.com
SUMMARY:Safeguarding datapath security requirements through formal verific
 ation
DESCRIPTION:Engineering Track Poster\n\nNicolae Tusinschi and Keerthi Deva
 rajegowda (SEDA)\n\nIn the fast-evolving landscape of modern computing, wh
 ere the exponential growth of data is ubiquitous, ensuring the confidentia
 lity and integrity of information stands as a paramount challenge. This pa
 per undertakes a comprehensive exploration of data security, employing the
  lens of formal security verification to address this critical concern. Th
 e study meticulously delves into the integration of cutting-edge tools and
  methodologies, strategically designed to fortify data security in the fac
 e of emerging threats. \nAt its core, this paper centers around the intric
 ate examination of data paths, driven by the imperative to eliminate poten
 tial vulnerabilities that could lead to leakage or corruption. Emphasizing
  the application of formal methods, the research identifies and mitigates 
 threats to data security, with particular attention to the detection of si
 de channels within processor architectures. This holistic approach extends
  beyond theoretical foundations, encompassing practical applications and a
 n in-depth exploration of formal modeling techniques, symbolic execution, 
 and advanced analysis methods, including static and dynamic analysis. The 
 paper ensures a dynamic exploration that seamlessly combines theoretical i
 nsights with practical applications, promising a comprehensive understandi
 ng of formal security verification.\n\nTopic: Back-End Design, Embedded Sy
 stems, Front-End Design, IP
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